ADI_AD9684BBPZ-500_PRPhotoRichardson RFPD Inc. announced the availability and full design support capabilities for a dual, 14-bit, 500 MSPS analog-to-digital converter from Analog Devices Inc.

The AD9684 includes an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The new ADC is specifically designed for sampling wide bandwidth analog signals. It is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.

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The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block.

The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting divide-by-factors of two, four and eight.

The AD9684 is suitable for a range of applications, including communications, diversity multiband/multimode digital receivers (LTE, 3G/4G, TD-SCDMA, W-CDMA, MC-GSM), general-purpose software radios, ultra-wideband satellite receivers, instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions), radar, digital oscilloscopes, high-speed data acquisition systems, DOCSIS CMTS upstream receiver paths, and HFC digital reverse path receivers.

The AD9684 is part of ADI’s Select Products for Q3, 2015.

According to ADI, additional key features of the AD9684 include:

  • 1.1W total power per channel @ 500 MSPS (default settings)
  • SFDR = 85 dBFS @ 170 MHz fIN (500 MSPS)
  • SNR = 68.6 dBFS @ 170 MHz fIN (500 MSPS)
  • ENOB = 10.9 bits @ 170 MHz fIN
  • DNL = +/-0.5 LSB
  • INL = +/-2.5 LSB
  • Noise density = −153 dBFS/Hz @ 500 MSPS
  • 1.25V, 2.50V, and 3.3V supply operation
  • 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)

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