Anritsu Company will showcase innovative high speed signal integrity solutions at DesignCon 2025, January 29-30 in Santa Clara, Calif. Anritsu (booth #907; Exhibit Halls A-D) will present live PCI-Express® 6.0 and 7.0 demonstrations of its industry-leading Signal Quality Analyzer-R MP1900A BERT in collaboration with Synopsys, Teledyne LeCroy and Tektronix to verify emerging high speed designs.
Live Demonstration (Anritsu booth #907)
PCI-Express® 7.0 Test Solution for Initial Verification with Synopsys’ PCIe 7.0 PHY IP – Anritsu, with Synopsys and Tektronix, will demonstrate a system featuring the Anritsu MP1900A MU196020A PAM4 PPG to transmit the required 64 Gbaud PAM4 signal over a long-reach channel to Synopsys’ PCIe 7.0 PHY IP receiver for preliminary PCIe 7.0 evaluation.
Additionally, Anritsu, using Synopsys’ PCIe 7.0 PHY IP and Tektronix’s RTO, will perform signal transmitter testing through SNDR measurements and waveform analysis at 128 GT/s. This integrated solution can be leveraged by engineers for initial PCIe 7.0 chip design and development with existing MU196020A PAM4 PPGs.
PCI-Express® 6.0 Differential Skew Evaluation – In collaboration with Teledyne LeCroy, Anritsu will also present a solution for evaluating the effect of differential skew in PCIe 6.0.
Transitioning to PAM4 signaling reduces eye size by more than 3x, thereby increasing margin sensitivity. Signals transmitting through a particular ISI channel cause a dip in the fundamental frequency due to the introduction of skew. While most BERTS do not natively support skew evaluation, Anritsu proposes using two MP1900A MU196020A PAM4 PPG units and the Channel Sync function to inject P-N skew.
Collaboration Partners
Synopsys – Network with Synopsys’ experts at partner booths and see next-generation interoperability demonstrations of Synopsys’ best-in-class 224G Ethernet IP and PCIe 6.0/7.0 IP.
The broad Synopsys IP portfolio includes logic libraries, embedded memories, interface IP, security IP, embedded processors and subsystems to accelerate IP integration and silicon bring-up. Synopsys’ IP Accelerated initiative provides architecture design expertise, hardening, and signal/power integrity analysis. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Teledyne LeCroy (Exhibit Halls A-D, booth #513) – Anritsu and Teledyne LeCroy share a common goal of providing engineers with early availability of highly accurate test solutions to verify leading-edge designs. At DesignCon 2025, they will be showing their joint solutions for high speed serial data validation, including fully-integrated automated receiver and transmitter test for PCI-Express 6.0 and USB4. In addition, Teledyne LeCroy will demonstrate cross-layer physical and protocol debug of PCIe 6.0 and USB4 interfaces, PCIe 7.0 transmitter characterization, and DDR5/LPDDR5 analysis and debug tools.
Teledyne LeCroy manufactures advanced oscilloscopes, protocol analyzers and other test instruments that verify performance, validate compliance and debug complex electronic systems quickly and thoroughly. Since its founding in 1964, the company has focused on incorporating powerful tools into innovative products that enhance “Time-to-Insight.” Faster time to insight enables users to rapidly find and fix defects in complex electronic systems, dramatically improving time-to-market for a wide variety of applications and end markets.
Tektronix (Exhibit Halls A-D, booth #819) – Visit Tektronix int booth #819 to experience the latest innovations in testing for compliance, power and memory as you connect with experts. Learn how to streamline PCIe Gen6/7 validation testing, automate test at 64 GT/s for PCI-Express 6.0 CEM Tx or Rx, or explore pathfinding of 128 GT/s measurements for PCIe 7.0 base specification. See how to streamline USB4v2 validation at 40 Gbps and how to empower engineers with a unified DDR5 DRAM Tx/Rx test workflow.
Demonstrations include how to optimize power and signal integrity for GenAI data centers to achieve energy efficiency with improved PI/SI measurements. Tek experts will show how to enable networking for AI/HPC interconnects by accurately testing 800G PHY transmitter conformance. Visitors will also learn about scaling high-power battery testing with a flexible platform that adapts to any power test application.