Capacitance is a part of every circuit design, whether intended or not. Chip capacitors are available in a wide range of sizes for every function from blocking DC to filtering microwave signals. But as small as they are, chip capacitors still occupy valuable area on a printed-circuit board (PCB), and mounting them—even by machine—can be labor intensive and time-consuming. For these and several other reasons, a method for fabricating PCBs with embedded capacitance provides a way to simplify and miniaturize some circuit designs. But is it right for your design?

As RF/microwave engineers know, discrete or surface-mount-technology (SMT) capacitors are one of the realities of PCB design, and for many circuits requiring relatively large-valued capacitors, they cannot be eliminated. But in many multilayer circuit designs, where power distribution to both analog and digital circuitry and devices is critical, and where small-valued decoupling or bypass capacitors help suppress noise, it may be possible to effectively create lower-valued capacitances between the layers of the circuit board.

A certain amount of intrinsic capacitance results from the spacing between the power and ground planes in a multilayer PCB, but this capacitance has typically been too small to be of practical value for decoupling purposes. However, by reducing the spacing between the two planes, and filling the space with a dielectric substrate material of relatively high permittivity, the capacitance between the two planes can be significantly increased. After all, a capacitor is essentially two conductive plates (or planes) separated by a dielectric insulator. Such variables as the spacing between the plates or planes and the relative permittivity or dielectric constant of the insulator material will determine the capacitance of the structure. The capacitance is inversely proportional to the dielectric thickness between the power and ground planes, with thin dielectric layers providing increased capacitance and reduced board thickness.

PCBs designed with embedded capacitors offer numerous benefits, provided that the approach provides high enough capacitance values for an application of interest. The use of embedded capacitance can replace large numbers of chip and/or SMT capacitors on a PCB, and potentially provide higher reliability than a board with large numbers of chip capacitors. It can simplify assembly and testing, by eliminating so many discrete circuit elements, and can minimize issues related to placing discrete capacitors close to the leads of active devices mounted on a PCB. When discrete capacitors are eliminated, the parasitic inductances associated with the leads of those capacitors are also eliminated.

In addition, the use of embedded capacitors can enhance EMC performance compared to PCBs with large numbers of soldered chip or SMT capacitors. In multilayer PCBs, chip or SMT capacitors are often connected to the pin of an active device by means of a plated-through-hole (PTH) connection between circuit layers. With parasitic inductance added as a function of PTH length, long PTH connections can impact timing in digital devices and degrade power distribution.

Balancing these positive attributes, any cost and performance benefits derived from the use of embedded capacitance very much depend on the specific circuit design. For example, in a circuit requiring a small number of discrete capacitors, incorporating embedded capacitance into a PCB can extend the design cycle and add cost. It is not unusual to require several iterations of a circuit design with embedded capacitance before optimum or even satisfactory performance is achieved, further adding to design cost and time. Typically, three-dimensional (3D) electromagnetic (EM) simulation tools are used to model circuit designs with embedded capacitance, and such models must account for a large number of variables, including the effects of embedded capacitance dielectric layer thickness, permittivity, and dielectric loss on the embedded capacitance.

Embedded capacitance materials are available from a number of commercial suppliers, including FaradFlex® family of laminates from Oak-Mitsu™ (www.oakmitsui.com) designed to be added to packages or multilayer PCBs, and DuPont™ Interra™ HK 04 embedded passives material from DuPont Electronic Technologies (www2.dupont.com). In addition, Sanmina-SCI® Buried Capacitance® technology patent-protected and registered by Sanmina-SCI Corp. (www.sanmina-sci.com) is licensed to a number of circuit material suppliers.

Often, embedded capacitance can be added to a multilayer circuit design with the addition of a suitable dielectric prepreg material. For example, RO4450F™ prepreg material from Rogers Corporation is a popular choice to use as a bonding layer for multilayer PCB’s with embedded capacitance. The 4-mil-thick RO4450F™, permittivity is 3.52 ± 0.05 in the z-direction at 10 GHz, also with dissipation factor of 0.004 in the z-direction at 10 GHz. This prepreg material has been used in PCBs with embedded capacitance, with varying degrees of success depending on the other circuit materials comprising the PCBs. In general, the dielectric material for an embedded capacitance layer should exhibit a high dielectric constant or relative permittivity, with flat frequency response and low loss. This combination contributes to producing an embedded capacitance layer with evenly distributed capacitance and minimal parasitic inductance. In terms of RF signal performance, this translates into minimal signal loss, while for digital and distributed power applications, it helps minimize phase distortion and timing errors.

Careful consideration should be given to the tradeoffs in using embedded capacitance, such as the cost of the embedded capacitance materials (or prepregs), the added design complexity, and the possible need to increase the number of design iterations to achieve acceptable circuit performance. But given the possibility of eliminating hundreds of bypass capacitors, for example, a multilayer PCB with embedded capacitance might make sense.

Readers planning on attending DesignCon 2012 (www.designcon.com) January 31^stand February 1^stare invited to visit with members of Rogers’ Advanced Circuit Materials (ACM) group at Booth #810 in the Santa Clara Convention Center (Santa Clara, CA). And while at the event, don’t miss the talk by Rogers’ material expert, Dr. Al Horn III, “Measurement and Modeling of the Effect of Laminate Thermal Conductivity and Dielectric Loss on the Temperature Rise of HF Transmission Lines and Active Devices,” scheduled for January 31 at 11:05 AM as Session 5-TA4.

Do you have a design or fabrication question? John Coonrod and Joe Davis are available to help. Log in to the Rogers Technology Support Hub and “Ask an Engineer” today.