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Paul Colestock, RFIC EDA Product Planning at Agilent EEsof, talks about solving the RFIC Design for Yield and Verification Dilemma with GoldenGate in the Cadence Virtuoso design flow.
Paul Colestock, RFIC EDA Product Planning at Agilent EEsof, talks about solving the RFIC Design for Yield and Verification Dilemma with GoldenGate in the Cadence Virtuoso design flow.