Panasonic Corp. and Renesas Technology Corp. will concentrate their joint development functions for leading-edge SoC process technologies at the Renesas Naka site, in Hitachinaka City, Ibaraki Prefecture, Japan, which began operation of the site’s 28 to 32 nm process development line on October 1, 2009. The two companies, by concentrating their joint development functions at the Naka site with its 300 mm wafer line and providing a joint development structure, are developing 28 nm process technologies. They are targeting the start of mass production in the near future.
The two companies agreed joint development of next-generation SoC technologies in 1998 and have continued to develop semiconductor process technologies for the 90 nm, 65, 45 and 32 nm generations at the Renesas Kitaitami site in Itami City, Hyogo Prefecture. A result of this joint effort was the development of interconnect technology using both transistor technology that has a metal/high-k gate stack structure and ultralow-k materials for the 32 nm system SoC process and acquiring a firm target date for its application in mass production.
Furthermore, in July 2009, this collaboration completed development of an SRAM cell using a metal/high-k gate stack structure for the 28 nm process. Now, based on these results, the two companies will start operation of that line to carry out joint development of full integration technology using 28 nm process manufacturing technologies in the 300 mm wafer development line newly installed at the Naka site.
In the development line at the site, the two companies have installed new production equipment in addition to having transferred part of the development line equipment from the Renesas Kitaitami site. By carrying out this development in the wafer size that will actually be used in mass production, the two companies are aiming at achieving a smooth transition to mass production and reducing development costs and time. This will improve development and production efficiency.
