This paper presents a new compact and comprehensive design methodology for RF CMOS source degenerated cascode dual functionality low noise amplifier (LNA) and power amplifier (PA) for the IEEE 802.15.4 standard (commercially known as ZigBee). Due to the need to meet the far apart performance requirements of both the LNA and the PA, the proposed design methodology is based on simultaneous graphical visualization of the relationship between all relevant performance parameters and the corresponding design parameters. To demonstrate the effectiveness of the proposed methodology, a design example is presented. The simulated performance of the designed amplifier at 2.4 GHz satisfies both the requirements of the ZigBee LNA and PA with noise figure (NF) of 1.6 dB, input third-order intercept point (IIP3) of 6 dBm and a 1 dB compression point (P1dB) of -3.5 dBm. At the high input power of 0 dBm, the amplifier achieves 24 percent power added efficiency (PAE) with 8 dB gain and 22 mW power consumption.
Introduction
Over the years, the design of low noise amplifiers in CMOS technology has attracted the attention of many researchers. This is attributed to the rapidly improving CMOS technology as a result of transistor scaling. In designing a LNA the following should be considered: Power gain, noise figure, impedance matching, reverse isolation, stability, distortion and power consumption. On the other hand, the design of the power amplifier is the most challenging task in a wireless communication transceiver. This is attributed to the trade-offs between the DC power supply voltage, output power, power efficiency and linearity. In designing a PA the following should be considered: High transmitted power, low power consumption, power added efficiency (PAE) nonlinear amplifier characteristics and design parameters, like third-order input intercept point (IIP3), carrier-to-intermodulation ratio (C/I), the input 1 dB gain compression point (P1dB) and adjacent channel power ratio (ACPR). Therefore, the LNA and PA designers are in front of a difficult trade-off among the competing goals of high performance in both amplifiers. In modern wireless communication systems, these two amplifiers are designed separately. No attempt has been reported, so far, for combining the two amplifiers in one.
In the IEEE 802.15.4 (ZigBee) standard, since the output power requirement is relatively modest, it is possible to consider the design of a single amplifier block that can act as a LNA in the receiver chain and a PA on the transmitter side. This would reduce the power consumption, chip area and size leading to cost savings of the transceiver that is vital to the widespread utilization of the ZigBee standard. However, since the achievable performances of the LNA and the PA are mainly limited by the CMOS transistors' parameters and operating conditions, the selection and implementation of a design methodology, leading to the solution of several design problems, is the crucial point in the design of such a dual functionality LNA/PA.
This article presents a new design methodology for a dual functionality LNA/PA. The proposed design methodology is based on simultaneous 3D graphical visualization of the relationship between all relevant performance parameters and corresponding design parameters. In this regard, it is intended to generate and provide a set of design graphs that can be used by the designer. A design example is then presented to demonstrate the effectiveness of the proposed methodology and the quality of trade-offs it allows the designer to make.
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