The power density of large periphery III-N HEMTs can be as high as 5 W/mm,1–3 much greater than GaAs (1 W/mm) and Si LDMOS (0.8 W/mm). These devices can generate more power per unit area of chip, or equivalent power in a much smaller package. All power that is not delivered to the load is dissipated locally in the device as heat.
The source of the heat generation is Joule heating at the intersection of the high electric field and current found in the channel on the drain side of the gate. In general, the channel temperature should be kept to a minimum while under operation at peak performance for a particular application. The two main drivers in minimizing channel temperature are the RF efficiency and the thermal resistance.
The RF efficiency determines how much of the power is dissipated as heat, while the thermal resistance is a measure of a transistor’s thermal design and determines the device’s ability to remove the heat. In this article, the focus is on improved thermal design in order to minimize the thermal resistance. Readily available factors that influence the thermal resistance include device layout, substrate thickness and packaging material. All three of these areas are explored in this work.
The choice of desired mean time to failure (MTTF) is a primary limit on the peak allowable channel temperature. Device designs typically target a 150° to 200°C channel temperature under operation, which results in an MTTF comparable to existing technologies, such as Si LDMOS and GaAs PHEMTs.4 The thermal limitation due to the onset of intrinsic conduction in the silicon substrate occurs above this range of channel temperature.
Experiment
The two devices considered in this study consist of undoped III-N heterostructures, grown by metal organic chemical vapor deposition on high resistivity Si (III) substrates. The details of the epitaxial structure and processing have been described elsewhere.5 The packaged parts consist of a 36 mm transistor die attached to a high thermal conductivity Cu-Mo laminate (CPC) or a pure Cu single-ended, ceramic package, using a AuSi or AuSn eutectic attach process, respectively. The sources are grounded to the package base through backside vias etched in the silicon die. A two-stage internal matching network is used to transform the input impedance, while no intentional internal matching exists on the output.3
Two different thermal designs, labeled devices A and B, with the same total gate width are compared in this study. A top-down view of a standard die in a typical CPC package (without a lid), which corresponds to device A, is shown in Figure 1. Device B has the same overall appearance, but has a Cu package, a thinned Si substrate and a thermally enhanced device layout on the transistor die. The detailed characteristics of the two devices are listed in Table 1.
Finite element analysis (FEA) has been used to assist in the determination of the thermal resistance from the channel to the heatsink in a realistic operating situation. The entire thermal environment relevant to the device is included, neglecting radiation into the air. The simulation consists of the packaged part mounted to a 1 cm thick aluminum application board. The temperature of this aluminum block is held at 80°C. Both the aluminum block and elevated base plate temperatures are included to mimic the configuration used during IR measurement.
The use of FEA was necessary in order to simulate the full large periphery device, including the relatively large package and fixture. The model covers four orders of magnitude from the micron scale gates to the centimeter thick fixture. Effects such as long range gate coupling, and the 3D extent of the package and fixture are included. The CFD-ACE+ multi-physics solver, commercially available from ESI Group Inc.,6 was used in this work. The standard layout and the thermally improved layout were simulated and correlated to measurement.
An infrared (IR) measurement was used to calibrate the FEA model and to verify the designs. All the measurements are made with a Quantum Focus Instruments (QFI) InfraScope II thermal imaging system.7 The dissipated power was produced by a direct current (DC) bias. The drain voltage was held at 28 V and the gate voltage was varied to achieve different drain current levels and hence different power dissipations. The heatsink temperature is maintained at 80°C to reduce the background radiant energy.
First, an image using the 1x lens was taken to determine the location of the peak channel temperature and to check the thermal distribution across the entire device. A 15x lens with approximately 2.5 μm spatial resolution was then used to obtain the peak channel temperature. The temperature at the back of the package is measured using a thermocouple passing through an aperture in the fixture and contacting the bottom of the package. The thermal resistance is calculated from the channel to the back of the package/case (RJC).
RF measurements were made at 2.14 GHz with a standard load pull system using tuners from Focus Microwaves Inc. The RF characteristics were taken at a drain voltage of 40 V. The devices were biased in class AB with approximately 27.5 mA/mm quiescent drain current, and the input and output impedances were optimized to obtain maximum RF output power.
Discussion and Results
Thermal simulations were used to investigate the heat removal from the device in order to lower the channel temperature. A model of the packaged device and fixture, as described above, has been used to investigate the effect of substrate thickness, package materials and device layout changes.
As an outcome of the simulation effort, a next generation device was developed using a Cu package, a thinned 4-mil Si substrate and an alternative layout, based on interleaving tiled cells. The cells are arranged in two rows, which provide room to increase the gate-to-gate spacing to 50 μm, reducing thermal coupling, or interaction between adjacent heat sources. In addition, there is room to leave a 300 μm gap between cells to additionally reduce coupling.
Devices with this layout have been fabricated and tested in Cu packages and are labeled device B in this study. Device B represents a tradeoff between thermal performance, RF performance and manufacturability. Figure 2 shows the simulated and measured temperature images of the two devices. The top pictures show the IR images of the devices under DC bias to achieve a dissipated power density of 1.09 W/mm, while the bottom pictures show the simulated devices at the same power density. The thermal stage is held at 80°C for the measurement, but the case temperature is higher and varies with power dissipation level. A graph of the junction temperature versus power dissipated for devices of both varieties is shown in Figure 3.
The base plate temperature is maintained at 80°C for both cases. From this graph, excellent correlation between the simulation and measured values is seen for both devices A and B. Additionally, the improvement in thermal performance for device B is evident. Device A can only dissipate approximately 1.25 W/mm (45 W) before reaching a junction temperature of 200°C, while device B can dissipate approximately 2.5 W/mm (90 W) before reaching a 200°C junction temperature.
Frequently, the maximum operating temperature limit of the device is obtained from the requirement for MTTF. Using a three-temperature DC life-test, a MTTF greater than 107 hours has been extrapolated at 150°C for devices of the same variety as device A of this study.8,9 The MTTF is greater than 105 hours at 200°C. Both of these results can be seen in Figure 4.
When the peak channel temperature exceeds 225°C, the RF performance is noticeably affected. At this point, the heat generated at the channel is sufficient to raise a significant portion of the Si substrate to 175° to 200°C. The intrinsic carrier concentration, ni, of Si at 200°C is 8.9x1013 cm–3. This carrier concentration corresponds to an n-type resistivity of approximately 50 Ω-cm.
As a large enough portion of the substrate becomes less resistive, the onset of significant RF loss is seen. In Figure 5, a clear example of thermally limited performance, which is explained by the onset of substrate loss, is shown in device A. On the other hand, it also shows that the improved thermal design in device B does not reach this limitation. Figure 6 shows the corresponding calculated channel temperature for each device. The temperature is calculated at each point using the measured output power, gain, efficiency and thermal resistance (1.95°C/W and 0.85°C/W) obtained from IR measurement and simulation.
A primary consideration of the RF design is the efficiency with which the device utilizes its power input (DC and RF). All waste power is dissipated locally as heat. Other key RF design metrics are low parasitic resistance and output capacitance, both of which will increase the device output impedance and aid in high efficiency design. Of course, a wide variety of considerations in the RF design can lead one to sacrifice efficiency for other performance criteria.
Device A in this study, a design intended to meet WiMAX application specific linearity requirements, is operated in a severely backed-off condition producing only 18 percent drain efficiency (DE) and 6 W of output power (POUT) under operation. The typical power gain, G, is 12 dB for the WiMAX design, or 15.83 on a linear scale. The dissipated power (PD) is thus PD = POUT (1/G + 1/DE–1) = 27.7 W. Using the maximum rated thermal resistance of 1.95°C/W for this part, the temperature drop from channel to case, ΔTJC = PD RJC = 54°C. Assuming a case temperature of 80°C, this places the channel below the 150°C operating temperature target.
If device A is operated with a continuous waveform (CW), it is capable of 65 W with 45 percent efficiency and 9.5 dB gain. The dissipated power of PD = 86.7 W results in a temperature rise of ΔTJC = 169°C. When device A is operated in CW with a case temperature of 80°C, the device clearly violates the thermal limit of 225°C and suffers from reduced RF performance.
A device, such as device B in this study, which possesses a 0.85°C/W thermal resistance, has a ΔTJC = 73.7°C for the same CW performance levels. Device B would only have a junction temperature of approximately 155°C when operated under CW conditions and with 80°C case temperature. The improved thermal performance of device B allows it to operate with good RF performance and with an acceptable MTTF even under the most stringent conditions of CW operation and elevated case temperature.
Conclusion
A primary consideration of RF design is maximizing the efficiency of the device under the actual application usage conditions. Once the best possible efficiency for the application has been obtained, the inevitable waste heat must be removed to the outside environment as effectively as possible to keep self-heating of the device to a minimum.
Simulation provides an accurate and predictive support for the design effort. The first thermal limit to be considered is reliability and specifically keeping the operating temperature low enough to meet the application’s MTTF goal. A second thermal limitation exists, for devices on Si substrates, at a channel temperature of approximately 225°C for RF applications due to loss of isolation between ground and the RF signal caused by the onset of intrinsic substrate conduction.
This article has demonstrated the use of thermal simulation, thermal measurement and RF measurement to optimize the design of a device. The resulting device makes use of substrate thinning, layout changes and Cu packaging to reduce the thermal resistance by a factor of two, thereby enabling a high performing and reliable device capable of operation under CW drive with elevated case temperatures of 80°C.
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