In the last decade, there has been an evolution to mmWave applications (i.e., 24 to 100 GHz) for commercial, industrial, IoT, wireless connectivity and an array of automotive radars. This rapid growth of mmWave applications has created a demand for multilayer printed circuit boards (PCBs) with mmWave circuits. The transition to mmWave comes with many challenges for the printed circuit industry—primarily conductor geometries and materials, since the shorter wavelengths reduce feature sizes and magnify the relative tolerances inherent in the PCB manufacturing processes. This article aims to help engineers design mmWave PCBs with good manufacturability and consistent electrical performance and to avoid some common design errors. Considering all key areas of PCB design, we introduce critical dielectric and conductor material properties, along with manufacturing process challenges.
Controlling production costs can be a complex engineering challenge. Cost must be incorporated into the electrical design from the very start, since this is where materials, substrate architecture and PCB technologies are defined. Like all good engineering, the goal is to design a product meeting all performance requirements with high yield, accounting for all material and manufacturing tolerances—resulting in a trade-off between cost and performance.
Finally, conducting signals to different layers is a difficult problem at mmWave frequencies. Leveraging material properties and the manufacturing challenges, we show an example of the formation of various via structures for mmWave PCB applications. We introduce a surface mountable crossover component simplifying via formation that has several additional advantages. It facilitates rapidly changing architectures and conducting signals to different layers, addressing the impact on electrical performance.
PCB MANUFACTURING CHALLENGES
Figure 1 Lateral etch thickness for the foil reduction and advanced foil reduction processes.
Figure 2 Standard pattern plate process and MEAP.
Figure 3 VIPPO vs. wrap plating.
Figure 4 C2eT process.
mmWave wavelengths are the same order of magnitude as PCB geometries. Cost is another factor adding to design complexity, since many new mmWave products are for consumer applications where substrate production volumes range from tens of thousands to millions of units.
In its simplest form, printed circuits are fabricated using a photo imaging and chemical etching process. This is accomplished by taking a copper clad laminate or a multilayer laminate and drilling circuit holes. After drilling, the panel is electroplated, building up copper in the drilled holes and on the surface—about 2 mils thick when starting with half an ounce of copper foil. Next, a photo resist is applied to the surface, imaged through a photo mask using ultraviolet light and developed to expose the unwanted copper. The exposed copper is chemically etched, leaving a finished circuit. This is defined as a “panel plate” process.
Etching down to the dielectric also etches laterally into the side of the conductor, making the process generally unsuitable for RF/microwave applications: Both electroplated copper and the base foil must be etched to form the conductor, resulting in poor geometries and less than desired conductor tolerances.
To overcome the problems with panel plating, most circuits are fabricated using a “pattern plate process.” Instead of electroplating the entire panel surface, photo resist is applied over the base copper foil. Then, either a photo mask or laser direct imaging is used to transfer the circuit image to the resisted coated panel. After imaging and development, the areas exposed on the base copper foil will be electroplated, forming a circuit pattern with copper also in the drilled holes. To protect the circuit image and hole barrels from the final etch, tin is plated on top of the circuit image. Next, the photo resist is stripped, and the background copper foil is etched, followed by a tin strip, yielding a finished circuit. The pattern plate process provides better geometries and tighter tolerances than panel plating because only the base foil needs to be chemically etched, minimizing the lateral etch that alters the conductor side walls (see Figure 1).
mmWave designs operating from 60 to 100 GHz require improved conductor tolerances and corner radius specifications on antenna patches and inset feed lines. Several technologies have been introduced to achieve tighter etching tolerances. The first involves the reduction of the base copper foil thickness on critical layers by chemical milling. The base copper foil is reduced to less than half an ounce, which reduces etching time and improves conductor geometries, minimizing etching into the conductor sidewalls and etch compensation. A second approach developed for mmWave applications, which enables tighter tolerances; smaller, undercut and better resolution; is a modified etch additive process (MEAP). Much like the foil reduction process, MEAP takes advantage of thinner base copper; however, it uses advanced etching technology to produce an extremely uniform copper geometry after etching (see Figure 2).
Another factor often overlooked is the additional copper thickness, due to more complex via structures, impacting both conductor geometries and tolerances. Most advanced PCB structures incorporate more than just through holes. There are also blind vias, buried vias, micro-vias and “via in pad plated over” (VIPPO), which complicate the plating process. To create reliable via holes, the copper must be plated from the circuit pattern surface down the hole barrel and back to the termination surface. Known as “wrap plating,” the copper plating is continuous, with no grain boundary that can fail in thermal cycling or assembly. Wrap plating occurs by default with through holes, since all three surfaces are plated simultaneously. This is not the case with blind vias and VIPPO. Per the IPC-6012 specification, a panel plate is required to meet a minimum thickness of 0.0002 in. per wrap plating cycle (see Figure 3).
Designs at mmWave almost always have a requirement for VIPPO and or blind vias to one or more depths. The implication for simulation models is that the base foil now has an additional copper plating thickness of 0.0002 in. minimum per wrap cycle. The additional copper thickness affects the conductor resolution as well as the tolerance of the electrical design. For example, adding VIPPO adds one wrap plating cycle; two blind via depths adds two wrap plating cycles; etc. This must be addressed early in the design process.
A third process is introduced to maintain accurate dimensional tolerances and to overcome copper thickness variations. This process is a hybrid between a pattern plate and a simple foil print and etch. The concept is straightforward for circuit images such as patch antennas and filter transformers: they are photo imaged on the base copper foil, usually half an ounce or less, then etched. The etched features are not plated, having the benefits of a foil-only etch and a thickness tolerance based only on the base copper foil. Non-critical and solder locations are plated with a standard pattern plate process (see Figure 4). While this process, known as C2eT, adds cost from the extra process steps, it offers better electrical performance.
Table 1 compares the features and capabilities of these PCB process technologies.
Simulation is the most important tool in the design process, defining the acceptable tolerances that determine what process technology is needed for conductor formation, dielectric materials and copper foil selection. Simulation is critical for cost reduction and failure analysis, since both are studied in a virtual environment that provides results faster than building prototypes.
Raw Material Tolerances and Variation
Regardless of the manufacturing process, manufacturing tolerances must be considered: both the raw materials, such as substrate and copper foil, and the PCB manufacturing process. Besides lot-to-lot variations and panel-to-panel variations, tolerances are often assumed to be global; however, they are also localized. Substrate effective dielectric constant (εreff) varies locally from non-homogeneous dielectric and the copper foil. The design itself affects the outcome. For example, the locations of vias affects the plating consistency by causing non-uniform currents, and variations in the copper percentage compounded through several layers may create localized peaks and valleys, causing irregular effective substrate heights after pressing. PCB manufacturing introduces localized differences from etchant/plating flow patterns that depend on direction.
