A Wideband Chaotic Colpitts Oscillator With Negative Resistance Enhancement for UWB Applications

A wideband cascode chaotic Colpitts oscillator with enhanced negative resistance is demonstrated. The circuit is implemented with InGaP/GaAs HBT technology. The measured fundamental frequency is 2.7 GHz, and the output power spectrum covers the 3.1 to 5.8 and 6.1 to 9 GHz ultra-wideband (UWB) bands. Negative resistance degradation caused by the Miller capacitance is compensated with an optimized base inductor. The fundamental frequency and bandwidth of chaotic oscillation is improved versus a normal common-base oscillator by increasing the voltage swing between the junctions as well as the transconductance of the transistor. This design also reduces power consumption in the oscillation loop.

Chaotic signals are wideband, deterministic, non-periodic and random-like signals derived from nonlinear dynamic systems. They offer a number of attractive features, particularly for UWB applications.^{1, 2} Several chaotic signal generator design technologies have been proposed to meet bandwidth demands at microwave frequencies. One proposed technology is based on the chaotic Colpitts oscillator.³

Colpitts-based chaotic oscillators have received significant attention in the past decade,^4,5,6,7,8 but the performance of a typical chaotic Colpitts oscillator is constrained by the influence of transistor parasitics that limit its fundamental frequency f₀.⁵ To mitigate the influence of parasitics and to increase f₀, various design techniques have been proposed including the use of parasitics as parts of the oscillation loop,⁵ an addition of a series L and diode load to redistribute the effects of base-collector parasitic capacitance C_BC,⁶ and a cascode structure to reduce the Miller effect at C_BC.^7,8

Improved chaotic Colpitts oscillators have had limited success, however, in increasing f₀ and bandwidth, while lowering power consumption. To gain an in-depth understanding of the performance issues and to explore the use of advances in normal oscillator design techniques for chaotic circuits, it is essential to recognize the commonality as well as differences in normal and chaotic oscillator designs.

A non-chaotic Colpitts oscillator exhibits a sharp decrease in negative resistance at high frequencies due to the Miller effect at C_BC, limiting its maximum oscillation frequency.⁹ The effect appears in chaotic Colpitts oscillators as well. Unlike a normal narrowband oscillator, however, a serial resistor is often included in the oscillation loop of a chaotic Colpitts to satisfy the requirement for broadband chaotic oscillation. This leads to a low Q and high power losses in the loop. The broadband oscillation requirement in a chaotic circuit imposes the need for a higher negative resistance than in a normal oscillator. Thus, the challenge in a chaotic circuit design is to determine a proper and sufficient negative resistance for overcoming resonator losses in order to reach a start-up chaotic oscillation and optimize f₀.

A cascode chaotic Colpitts oscillator design is introduced with two separated inductors connected at the base and collector nodes respectively. Tuning of these two inductors enhances negative resistance to compensate for its degradation from the decrease of transistor transconductance (g_m) at high frequencies and maximizes the fundamental frequency f₀. The enhancement of g_m with base inductance reduces the need for a higher bias voltage and current, thus lowering resonator power consumption. Measurement results demonstrate operation from 1.3 to 9 GHz, covering the 3.1 to 5.8 and 6.1 to 9 GHz UWB bands.

CIRCUIT DESIGN

Figure 1a represents a normal chaotic Colpitts oscillator design,^7,8 while Figure 1b shows the new cascode chaotic Colpitts oscillator design. The chaotic circuit of Figure 1b evolves from a traditional normal common-base cascode Colpitts oscillator by including an additional inductor L_B at the base node. The bias current I_SS is controlled by tuning the voltage source V_SS. In contrast to a standard common-base chaotic Colpitts design,^4,6,7,8 this circuit has two important design features. First, the parallel equivalent inductance of L_C-R_C and L_B-C_BC is smaller than that of L_C and L_B. Without significantly impacting the fundamental frequency f₀, the g_m of the transistor can be enhanced by increasing L_B. Consequently, the negative resistance is enhanced by increasing the voltage swing between the junctions as well as the g_m of the transistor. Second, the enhancement of g_m with L_B reduces the demand for higher V_DD and I_SS, thus lowering power consumption of the oscillation loop.

NEGATIVE RESISTANCE ANALYSIS

Figure 2 shows the equivalent circuit of the chaotic oscillation loop in Figure 1b. The input impedance Z_in between base and collector nodes can be viewed as an equivalent circuit of a negative resistance R_in in series with a capacitance C_in.

R_in of the normal common-based circuit in Figure 1a can be expressed as:

R_in of the circuit in Figure 1b can be expressed as:

where C_BE and C_BC are base-emitter and base-collector parasitic capacitance respectively, f is the oscillation frequency of the loop; Q1 and Q2 are the same transistors.

When L_B = 0 nH,

Equation 5 shows that the equivalent circuits of the two chaotic oscillators in Figure 1 are the same without considering L_B. From Equations 2, 3 and 4, we can calculate the negative resistance R_in (2 µm InGaP/GaAs HBTs with f_T=29.5 GHz, CBE=0.49 pF and CBC=0.28 pF are used in calculation). Figure 3 shows the negative resistance Rb in dependenceon the ratio of L_B/L_C. Each curve is generated by fixing the value of L_C and the oscillation frequency. Ra in is a constant value with fixed oscillation frequency. When the L_B/L_C ratio equals zero, Rb in and Ra in are the same as shown in Equation 5. The equivalent circuit of L_B-C_BC is capacitive and its impedance is inversely proportional to L_B. When L_B is small, -Rb in increases with L_B because the impedance of L_B-C_BC is much larger than -Rb in and its decrease in value can be neglected. Thus, -R_in is mainly dominated by the transistor g_m, which is directly proportional to L_B and the voltage, current swing in the circuit. However, when L_B is large, -R_b in decreases as L_B increases, because the impedance of L_B-C_BC is too low to be neglected and the voltage and current swing and gm enhancements become saturated. -R_b in is mainly determined by the impedance of L_B-C_BC, decreasing with increasing L_B. An optimum L_B/L_C ratio is observed for the maximum negative resistance. When L_B is 2 to 3 times L_C, -Rb in is improved by almost 50 percent over -Ra in. Therefore, with an optimum L_B/L_C ratio, L_C, C₁, C₂ and C₃ are reduced to increase the chaotic oscillation frequency.

Figure 4 shows the simulated output power spectrum of the circuit. Transistors used in this simulation are the same as aforementioned InGaP/GaAs HBTs. When L_B/L_C=0, the highest fundamental frequency f₀ for chaotic oscillation is only 2 GHz. When L_B/L_C=2, f₀ increases to 4.5 GHz. When L_B/L_C = 3, f₀ decreases to 3 GHz. From these simulation results, an optimum L_B/L_C ratio is observed for the maximum fundamental frequency f₀, which is consistent with calculated results in Figure 3.

MEASUREMENT RESULTS

The proposed cascode (with L_B) and the normal common-base (without L_B) chaotic Colpitts circuits are implemented with 2 µm InGaP/GaAs HBT technology. Figure 5 is a photograph of the fabricated 0.6 × 0.6 mm chip. As chaotic circuits are extremely sensitive to circuit elements, L_B, L_C and R_C in Figure 1 are not designed into this chip, enabling adjustment of L_B, L_C and R_C values on the PCB to fit chaotic oscillation start-up conditions.

To optimize the fundamental frequency, f₀, the values of the loop inductances L_C, L_B, capacitances C₁, C₂, C₃ and the loss resistance R_C are chosen based on the concept previously outlined. Note that the effect of parasitic base-emitter capacitance C_BE has been considered in choosing capacitance. V_DD is fixed and V_SS is adjusted to achieve the desired output chaotic signals. Figures 6a and 6b show the measured output power spectrum of the normal cascode circuit without L_B and the proposed circuit with optimized L_B, respectively. In Figure 6a, L_B = 0 nH, L_C = 5 nH, R_C = 25 Ω, C₁ = 3 pF, C₂ = 3 pF, C₃ = 3 pF, V_DD = 10 V, I_SS = 16 mA and f₀ = 1.6 GHz. In Figure 6b, L_B = 2.7 nH, LC = 1.3 nH, R_C = 22 Ω, C₁ = 2 pF, C₂ = 2 pF, C₃ = 2 pF, V_DD = 7 V, I_SS = 12 mA and f₀ = 2.7 GHz.

The optimum L_B of 2.1 times L_C is consistent with calculated results in Figure 3 and simulation results in Figure 4. The fundamental frequency f₀ is 1.6 GHz and 2.7 GHz for circuits without L_B and with optimum L_B, respectively, illustrating an increase in f₀ of 69 percent. Using the chaotic bandwidth (BW) definitions in Mykolaitis et al.,⁴ and Bumeliene. et al.,⁸ frequency bands of the output power spectra are: Band 1: 1.3 to 2.7 GHz, Band 2: 2.9 to 5.8 GHz and Band 3: 6.1 to 9  GHz as shown in Figure 6b. Band 2 and Band 3 cover the 3.1 to 5.8 GHz and 6.1 to 9 GHz UWB bands respectively. Wire inductance and parasitic resistance on the circuit board may be causes for a lower measured f₀ than simulated.

Figure 7 shows the double scroll attractor of the proposed circuit measured with an oscilloscope. Circuit elements are the same as in Figure 6b. The horizontal axis (200 mV/div) represents the collector voltage of Q1 and the vertical axis (100 mV/div) is the base voltage of Q1. The double scroll attractor confirms that the oscillation is chaotic.

Table 1 compares the performance of this design with recently published microwave chaotic Colpitts oscillators.^4,6,8,10 The fundamental frequency f₀ for this design is much higher. Excluding power consumption of the current source and output buffer, the loop power consumption (LPC) is estimated by (V_DD+0.8 V) × I_SS in a Colpitts circuit using BJTs and by (V_DD+1.6) × I_SS in a Colpitts circuit using HBTs. LPC in this design is much lower compared to the others represented in the table.^4,6,10 This power reduction is attributed to an increased g_m with an optimum base inductor alleviating a sharp decrease at reduced bias voltage V_DD and current I_SS.

CONCLUSION

A cascode Colpitts oscillator with enhanced negative resistance is designed for the chaotic oscillator. Theoretical calculation shows that the negative resistance degradation at high frequencies is compensated by increasing the voltage and current swing in the circuit and the transconductance of the transistor via an optimum base inductor. With enhanced negative resistance, the fundamental frequency f0 is increased to 2.7 GHz. The circuit operates from 1.3 to 9 GHz, covering the 3.1 to 5.8 and 6.1 to 9 GHz UWB frequency bands. This design also reduces power consumption in the oscillation loop.

ACKNOWLEDGMENTS

This work was supported by the National Science Foundation of China under Grant No. 11074122.

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