Growing demand for high performance RF, microwave and serial communication devices (SERDES) has highlighted the need for good signal integrity (SI) in modern designs. Engineers need to accurately characterize timing, jitter and noise performance to determine the operating envelope of their designs and guarantee reliable operation once deployed.
Validating SI has traditionally been a specialist task requiring high-end oscilloscopes that can be both expensive and bulky. Real-time digital oscilloscopes, above 10 GHz, are suited to debug and troubleshoot tasks, and can be used to check signal integrity. However, they tend to be expensive and suffer from drawbacks – including limited 8-bit ADC resolution, reduced to 6 bits or less at high frequencies – and relatively high intrinsic jitter floor.
For cyclic signals, or repeating patterns, sampling scopes offer wide bandwidth for lower budgets and benefit from low intrinsic jitter and noise, and voltage resolution down to 100 µV or better. Those capabilities, combined with measurement analysis and visualization tools, make the sampling scope a potent tool for device characterization and identification of signal integrity issues.
Most sampling scopes employ a large mainframe with sampling heads on extender leads that can be placed close to the device under test. This complexity is not necessary with the PicoScope 9300 Series scopes, as their small size allows the user to position them right next to the device under test.
Figure 1 The PicoScope 9302 set up to measure characteristics of a 2.5 Gbit/s PCI Express card using a 'break-out' box with SMA connectors to access clock and data channel.
With 20 GHz bandwidth, the scopes can acquire signals with rise times down to 17.5 ps. Precise time-base stability and accuracy, and timing resolution as low as 64 fs, allow characterization of clock timing and jitter in demanding applications.
PicoSample 3 software gives control of the scope and numerous predefined trace, eye and statistical measurements. The software includes 167 standard serial data communications masks with user margin, editing and custom mask compilation. Advanced tools such as a color-graded persistence display, histograms and pattern-lock triggering give more insight into waveform characteristics plus jitter and noise distribution.
In the test setup shown in Figure 1, a PicoScope 9302 has been set up to measure characteristics of a 2.5 Gbit/s PCI Express card using a ‘break-out’ box with SMA connectors to access clock and data channels. The PicoScope 9300 is small enough to be placed close to the device under test to ensure good measurement fidelity.
For the practical example, the first task is to characterize the clock signal. A dedicated frequency counter shows the trigger signal frequency at all times, regardless of measurement and time-base settings. Automated measurements have been enabled to show frequency, rise time and jitter (peak-to-peak) as shown in Figure 2. Measurement statistics can be used to analyze long-term signal behavior as a predictor of system reliability.
Next, the characteristics of the data channel can be examined by building an eye diagram (shown in Figure 3) and measuring key parameters such as the eye height and width, and jitter – a key parameter to control with designs operating in the Gbit/s range and higher. Note that the device under test has been programmed to output a pseudo-random bit pattern to represent real-world operating conditions. Eye diagram testing can be automated using masks defined for the transmission standard in question. Note also that a color-graded display is being used to give a visual indication of frequency of occurrence of waveform paths, which gives important clues about error types and their sources.
Figure 2 Automated measurements show frequency, rise time and jitter (peak-to-peak).
Figure 3 An eye diagram can be used to construct the characteristics of the data channel.
In Figure 4, the eye diagram has been complemented with a histogram of the waveform crossing points. Histograms show distribution of jitter (or noise) in a high speed design, which give important clues about the jitter components and their source: pattern-dependent (bounded) and random components can be isolated and tackled in the design.
Figure 4 The eye diagram has been complemented with a histogram of the waveform crossing points.
Figure 5 The histogram can be used to 'slice' the waveform to reveal subtle details and offer an insight into the waveform behavior.
If a design appears susceptible to error under certain bit sequences, the pattern lock trigger can be used to isolate only the preceding pattern that is causing the problem and to display it in an Eye Line diagram. As Figure 5 shows, the histogram can be used to ‘slice’ the waveform to reveal subtle details and offer an insight into the waveform behavior, helping the designer to focus on sources of error.
Low-jitter clock distribution and high speed data pathways are at the heart of today’s wireless infrastructure, consumer electronics, broadband and other applications. PicoScope sampling scopes are ideal for critical analysis and verification of high performance waveforms, giving the designer confidence to sign off a design before moving it into production. PicoScope 9300 Series scopes are physically small, to preserve SI close to the device under test and low cost.
Pico Technology,
St Neots, UK
+44 1480 396 395,
www.picotech.com