SANTA CLARA, Calif., June 25, 2009 -- Agilent Technologies (NYSE: A) today announced validation of its GoldenGate RFIC simulation, analysis and verification tool to accelerate RF readiness for STMicroelectronics' 32 nm RF CMOS technology. The qualification of GoldenGate for STMicroelectronics' 32 nm RF technology is the result of a long-term collaboration between the two companies that includes 65 nm and other market-critical processes.
"Our successful track record with GoldenGate allowed us to start optimizing 32 nm RF IP designs early in our technology development cycle with a comprehensive AMS/RF Physical Design Kit and CAD solution," said Vincent Varo, CMOS and derivative process design kit manager, Technology R&D, STMicroelectronics. "These designs include best-in class RF devices (RF MOS, MOM, inductors and varactors) offered with suitably qualified SPICE models, simulation environment, layout PCells and physical verification (DRC/LVS-PEX) tool-suite. With time-to-market such a critical component in recouping the investment in leading-edge technologies, having a head start on complex RF blocks is invaluable."
"Having the right tools is often not enough to be competitive these days," said Thierry Locquette, Global EDA account manager with Agilent's EEsof EDA division. "You also need the confidence to deploy them during the early phases of the technology development cycle. This kind of confidence comes from having past successes and is a byproduct of making the investment to build relationships like the one we have established with STMicroelectronics."
Agilent's GoldenGate software is an advanced simulation and analysis solution for integrated mixed-signal RFIC designs. Its unique simulation algorithms are optimized for the challenging demands of today's complex RFICs, and its capacity enables full characterization of complete transceivers, including parasitics, prior to tape-out. GoldenGate also includes a suite of automation tools developed with the RFIC designer in mind. This suite helps designers easily launch simulations, quickly analyze circuit performances and diagnose problematic issues with mixed-signal RFICs earlier in the design cycle.
