Pat Hindle, MWJ Editor
Pat Hindle, MWJ Editor RSS FeedRSS

Hindle
Pat Hindle is responsible for editorial content, article review and special industry reporting for Microwave Journal magazine and its web site in addition to social media and special digital projects. Prior to joining the Journal, Mr. Hindle held various technical and marketing positions throughout New England, including Marketing Communications Manager at M/A-COM (Tyco Electronics), Product/QA Manager at Alpha Industries (Skyworks), Program Manager at Raytheon and Project Manager/Quality Engineer at MIT. Mr. Hindle graduated from Northeastern University - Graduate School of Business Administration and holds a BS degree from Cornell University in Materials Science Engineering.

IBM to Publish 2 GHz Graphene IC at Upcoming Conference

September 21, 2011
IBM is set to publish a paper on a 2 GHz frequency doubler RF circuit in a CMOS-compatible manufacturing process technology at the upcoming International Electron Device Meeting, due to be held in Washington DC, Dec. 5 to 7. IBM researchers will deliver a paper that is a significant step toward moving graphene from the lab into a manufacturable technology. It will detail how using a 200 mm wafer-scale CMOS-compatible fabrication process can be used to make high-performance graphene FETs and RF passives.


A major obstacle with graphene is the difficulty of building a gate dielectric (insulating layer) on its inherently inert surface. However, graphene layers grown by controlled vapor deposition (CVD) can be transferred to many types of substrates. To take advantage of this property, IBM built silicon wafers containing pre-defined embedded gate structures, and then transferred CVD-fabricated graphene layers onto them. As an example they built a frequency doubler which demonstrated a conversion gain of ~-25 dB at an output frequency of 2 GHz. This performance was nearly constant from 25-200°C, indicating that both n- and p-transconductance are temperature-independent in this range, a new finding for CVD graphene-based devices.



The four images on the right show (a) an 8” graphene FET wafer; (b) single die; (c) SEM image of a typical fully processed device and (d) an enlarged view of the device showing the embedded gate structure with two-finger design. Except for the CVD graphene transfer, all processing was done in a conventional 200 nm fab. Graphene technology is finally making it into production.

You must login or register in order to post a comment.