Judy Warner
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Judy Warner is the western regional and RF/microwave market director of business development for Zentech Manufacturing, a contract manufacturer that offers fully integrated supply chain solutions for mil/aero, RF/microwave and medical markets. Zentech is based in Baltimore, MD near the high technology corridor of the Mid-Atlantic/Pentagon region. Judy has over 20 years of experience in the electronics industry, and has spent the past four years focused exclusively on RF and Microwave technology solutions. Judy also sits on the advisory board of eSurface technologies and contributes articles to a variety of microwave and electronic industry trade publications, including 3 years as a contributing guest blogger for Microwave Journal.

Simulations That Don't Add Up

November 23, 2011

Microwave Journal

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Before I begin my blog-rant, let me wish you and yours a very happy and healthy Thanksgiving! While I hope you enjoy your holiday, and stuffing yourself with turkey, I wouldn’t want you to look like a turkey at work. So, I thought I would share a bit of insight offered to me recently. As I mentioned in an earlier post, my friend Michael Ingham of Spectrum Integrity and I recently spoke at PCB West, and co-authored a paper to discuss some of the challenges of RF/MW PCB Design and Fabrication. Michael helped me to understand one of the reasons why simulations don’t match the measured performance of a PCB after fabrication. It is a rather simple concept, but one often overlooked. Here is an excerpt from our paper:

Performance not matching simulations

Advanced designs with RF and ultra high-speed signals frequently undergo extensive simulation and analysis during the design phase. It is not uncommon for simulation data to not match measured data from a finished PCB. One item of disconnect often seen is that engineers set up their simulation models using a copper thickness based on which copper thickness is called out, such as ½ oz, 1 oz, etc. The factor that often gets overlooked is when plated-through-holes get plated, this plating also gets added to the PCB outer layers. Since plating is a wet process where the manufacturing panel is immersed in a chemical bath for plating, plated holes typically get 0.001 of copper, and the outer layers also get this copper added. So if simulations are based on a ½ oz copper thickness (which is approximately 0.067), the actual finished thickness can be 2X, or more, due to the hole plating process and this isn’t being accounted for in the simulation model. This can throw off simulation data and impact designed etched features such as transmission lines, filters, coupled lines, etc.

A simplified graphical illustration of plating effects can be seen in Figures 3 and 4 below. Figure 3 shows a section of a 4 layer PCB with a drilled hole prior to hole plating. Figure 4 then shows the resulting plated hole and this extra plating being added to the outer layers. (the plating metal is shown as gold just for illustrative purposes) .

With sequential lamination cycles, the effects can be more dramatic such as blind vias being exposed to multiple plating cycles. Figures 5 through 8 provide an example of plating effects due to multiple plating steps. The different colors of the metal shown below, gives a visual representation of the cumulative plating effects.

So, when creating your simulations, be sure to factor in the additional copper thickness that will be added to any critical layers due to hole plating. If you are not sure, consult with your fabricator who will be able to advise you of the impact plating will have on your specific product.