NEC Corp. (NEC) and NEC Electronics Corp. (NECEL) have successfully developed the Low-Power Low-Noise All-Digital Phase Lock Loop (ADPLL) LSI. The newly developed LSI is suitable for midget wireless equipment yielding a long operation lifetime for small-sized batteries. It also features low-phase noise, which is vital to many modern wireless systems, including Bluetooth, ZigBee, WiFi and WiMAX.
The key building block of the ADPLL, the Time-to-Digital Converter (TDC), has a new architecture that can achieve high accuracy in time-domain signal processing with reduced power consumption; the novel architecture is based on a fine/coarse two-step phase comparison scheme that can greatly reduce the number of circuit elements to be powered in each timing-comparison step.
Using such a scheme, only a fraction of the PLL circuit is powered, minimum time is required and the other circuits are automatically shut down. Meanwhile, in order to achieve a low phase noise for ADPLL, another novel design is employed that intentionally adds a random signal to the oscillator. This approach drastically suppresses undesired noise originating from digitally periodic control. Based on these two developments, the digital PLL technique is now made applicable to a high-speed wireless system that simultaneously requires low-noise and extremely low-power performance.
These results can also be applied to RF chips in support of any wireless standard. NEC and NECEL will continue to pursue research and development in this area towards early realization of small wireless equipment with long battery life.
