There are many design considerations involved. The phase noise of the oscillator directly impacts the system’s overall performance. For example, the phase noise of the VCO affects the cell phone receiver adjacent channel rejection performance. Its current consumption is a major part of the overall receiver power budget as in a low power GPS receiver. Since an inductor is used in the oscillator design, the real estate of the oscillator is a high percentage of the overall IC. There are many design topologies available to the designers. There is no single design that will fit all the requirements. It is the designer’s job to determine the most suitable topology based on the applications and requirements. This article is intended to present four commonly used CMOS oscillator topologies. Their theory of operations is presented and their pros and cons are discussed in detail.
The first topology presented is an inductor-less, generic, three-stage ring oscillator. The ring oscillator typically has an odd number of stages to prevent latch up. Each stage provides an equal amount of the gain and phase shift needed. Its schematic is shown in Figure 1. It is a much simpler circuit than it looks. This circuit contains three identical gain stages. M1 to M6 forms the first gain stage. To further simplify the analysis, only the left half of stage 1 is examined. M1 is the NMOS that provides the gain. M4 is essentially a diode-connected PMOS load. M3 is used as a trick to enhance the gain. The gain of the diode-connected load amplifier depends on the geometry of both NMOS and PMOS. The gain equation is
where
W/L = channel width over channel length ratio
In order to get a higher gain, W/L for the PMOS device needs to be small. However, this will result in a higher overdrive voltage for the PMOS device since the bias current is fixed. Thus, it will reduce the voltage swing at the drain of the PMOS and NMOS transistors. The trick is to bias M3 to “steal” part of the bias current that has to flow in the PMOS. This way, a compromise is reached between voltage gain and voltage swing range. M2, M5 and M6 provide the other half of the differential gain stage. The first gain stage is repeated three times to complete the overall ring oscillator. The outputs of each stage are taken at the drains and the inputs are located at the gates. The positive side of the output drives the positive input of the next stage. The exception happens at the last stage where the positive output drives the negative input. The reason is that each gain stage provides a 60° phase shift at the frequency of operation. The three stages provide a 180° phase shift. The remainder of the phase shift comes from the output inversion. The frequency tuning is done by controlling the bias current. The most attractive feature of this topology is that no inductor is used. It saves a large amount of real estate. The design is also very simple to implement since identical gain stages are used. No varactor design is needed since the frequency control is accomplished by varying the bias current. The best feature of this topology is also the root of its problem. Without an LC filter bank, the phase noise performance is much worse.
To improve the phase noise performance, an oscillator with an LC tank is typically preferred. Its basic form is presented in Figure 2. The basic idea is based on negative resistance theory. An oscillator can be reduced to a simple parallel RLC (resistor, inductor and capacitor) circuit. In an ideal oscillator, the parallel resistance should be infinite. The energy is transferred back and forth between the inductor and the capacitor. A positive resistance means that some of the energy will be taken away by the resistor and dissipated as heat. If the positive resistor takes energy, then a negative resistor must provide the energy to sustain the oscillation. This is the fundamental idea of this topology. M1 and M2 form the VCO core. By cross coupling M1 and M2, the positive feedback provides a negative impedance looking back into the drain of M1 and M2. The negative impedance is given by
where
gm = transconductance of the NMOS
Here, the varactor tuning diode is represented by a variable capacitor. L1 and L2 each form half of the inductance for the LC tank. M3 and M4 are the source followers. They are the output buffer to help lower the output impedance in order to drive the mixer efficiently. This topology is easy to understand and relatively easy to implement. It offers good phase noise and good tuning range. It has been a very popular topology for the oscillator designer. There is still room for improvement in the area of power efficiency. This will lead to the third oscillator topology.
The third oscillator topology, shown in Figure 3, is typically labeled a complementary cross-coupled oscillator. It gets its name because both NMOS and PMOS devices are used to obtain the negative resistance. M1, M2, M5 and M6 are the active elements contributing to oscillation. M3 and M4 are the output buffers. During half the cycle, M1 and M6 are on while M2 and M5 are off. The full bias current flows through the RLC network. Vice versa, during the other half of the cycle, M2 and M5 are on while M1 and M6 are off. This is the major difference between the cross-coupled oscillator and the NMOS-only cross-coupled oscillator. Note that the sum of L1 and L2 in the NMOS-only cross-coupled oscillator is equivalent to L1 in the complementary cross-coupled oscillator. In the NMOS-only design, during each half cycle of the oscillation, the bias current only flows through one half of the inductor. Because of this, the cross-coupled design has many advantages over the NMOS-only. First, the cross-coupled oscillator is twice as power efficient as the NMOS-only design. Second, the voltage swing in the cross-coupled oscillator is twice that of the NMOS-only oscillator, which improves the phase noise by 6 dB. Thus, the cross-coupled oscillator is becoming the oscillator of choice by more and more designers.
There are many design variations derived from the complementary cross-coupled oscillator topology. One topology is to eliminate the bias current source. Voltage bias at the gate of the active element is used instead. The bias current source is typically implemented with a current mirror. Without the NMOS for a current mirror, the design will gain extra overdrive voltage swing headroom. The downfall is a higher power consumption because of the higher voltage swing needed to drive the transistor. The other improvement includes adding an AC ground capacitor at the source of the FET. The idea is that the virtual ground at the source is not perfect. It has been reported to improve phase noise. The cross-coupled oscillator has its disadvantage as well. Because the PMOS performance is typically lower than the NMOS for the same geometry, the upper frequency range will be compromised compared to an NMOS-only topology. Since the transconductance of the PMOS is lower than the NMOS, proper scaling is required. Otherwise an asymmetrical waveform will result.
The topologies of the cross-coupled oscillators can be used as a building block for a more advanced oscillator. In most wireless devices using digital modulation/demodulation, both I and Q channels are required. Traditionally, an oscillator is designed and then an extra device is used to convert the oscillator output to an I/Q signal path. In many IC designs, an RC network is used to get I/Q. However, a one-stage RC network has a very limited frequency range. It is not suitable for today’s wideband, multiple-band, multiple-mode, highly integrated transceivers. To improve the frequency range, multi-stage RC polyphase filters are used. But the issue is high insertion loss through the RC network; hence, the power efficiency suffers. A better design is to use a quadrature VCO (QVCO), as shown in Figure 4. The QVCO is based on the idea of sympathetic oscillation. With proper coupling, a pair of VCOs can oscillate in harmony. An NMOS-only oscillator is used as the basic building block. M1 to M4 along with the LC tank form the first oscillator. M5 to M8 complete the second oscillator. M1, M2, M5 and M6 are the negative resistance generating active elements. M3, M4, M7 and M8 make up the output buffers. The circuit design itself is straightforward once the individual VCO design is under control. Compared with the polyphase RC network-based I/Q generation, QVCO is far more efficient in power and space. One area that needs to be watched is bimodal oscillation. Basically the QVCO will oscillate either with 90° phase shift or –90° phase shift. Both phase shifts satisfy the oscillation requirement. Bimodal oscillation is highly undesirable. It can be resolved by introducing a proper phase shift in the buffer driver circuit. By using a cascade topology in place of the M3, M4, M7 and M8, bimodal oscillation is eliminated.1
Conclusion
This article has presented commonly used CMOS oscillator topologies. Each topology has its own advantages and disadvantages. There are many tradeoffs involved as in most RF designs. For applications with tight space requirements and relaxed phase noise, the ring oscillator is a good choice. For best power efficiency, the cross-coupled oscillator deserves strong consideration. For simplicity and higher frequency operation, the NMOS-only oscillator is still a good candidate. All the basic oscillator topologies can be reused in a more complex design like the QVCO. There are still many practical design considerations involved in inductor and varactor designs. With so many design choices, oscillator designers need to choose the right topology based on the application at hand.
References
- S. Li, I. Kipnis and M. Ismail, “A 10 GHz CMOS Quadrature LC-VCO for Multi-rate Optical Applications,” IEEE Journal of Solid State Circuits, October 2003.
- B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, NY, 2001.
- H.T. Lin, Y.K. Chu and H.R. Chuang, “A 2 GHz, 0.25 mm CMOS Complementary VCO with Differentially Tuned MOS Varactors for Wireless Applications,” Microwave Journal, Vol. 49, No. 4, April 2006, pp. 94–102.
- A. Rogougaran, J. Rael, M. Rofougaran and A. Abidi, “A 900 MHz CMOS LC Oscillator with Quadrature Outputs,” Proceedings of the 1996 International Solid State Circuits Conference.
Louis Fan Fei received his BSEE and MSEE degrees from Georgia Tech in 1996 and 1998, respectively. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He also worked on microwave instrument circuits for HP/Agilent in Colorado Springs, CO, in the summer of 1997. He is now an RF engineer at Garmin International, where he designs GPS receivers.
