Current research studies are drawing more and more attention on the memory effects of high power amplifier linearization, especially for cellular base transceiver system applications.1,2 Although many studies on power amplifier linearization have been conducted, linearization of strongly nonlinear systems with large memory, which exacerbates the performance of the linearizer, still gives rise to many challenging issues related to the complex nonlinear distortions caused by the memory.3–9
There are two kinds of predistortion techniques: one is based on analog circuits and the other on digital circuits. The analog predistortion methods, when applied to WCDMA systems, have a limited linearization ability (5 to 10 dB) due to their poor flexibility on functional representations and their insufficient capability in the memory effect compensation, while the cost of the circuits is relatively low. Therefore, it has been difficult to make a high power amplifier with an analog predistorter meeting the 3GPP system’s linearity specifications.9 On the other hand, the digital predistortion method has been regarded as a promising candidate for a low cost linearization method, thanks to its more precise compensation capability for the complex nonlinear behavior of the high power amplifiers. Furthermore, as the resolution and the sampling speed of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) get higher and faster,10,11 digital predistortion methods gain greater value for commercial use.
Various behavioral modeling methods for RF power amplifiers have been developed using many different functions or algorithms, such as a Volterra filter, Weiner filter, memory polynomial, auto-correlation and various types of neural networks.10–20 They have been mainly used for communication system simulation. Recently, researchers have begun to apply artificial neural networks to baseband behavioral modeling of RF high power amplifiers and even to digital predistortion techniques, due to advantages such as the fast nonlinear analysis, high reusability and the versatility for arbitrarily nonlinear systems.21,22 Since the basic neural network structure is not sufficient to reflect the memory effects in modeling, reinforced neural network methods with delay taps (that is tapped delay neural networks or TDNN) have been introduced.22 Because the algorithm for digital predistortion requires a very accurate baseband equivalent model for the power amplifier, an exact behavioral model, including memory effects, should be developed as the first step in the power amplifier linearization procedure. Time and effort can be saved if a standardized procedure for the digital predistorter construction is available as well as an outstanding linearization algorithm.
In this article, an effective linearization procedure is developed, adopting TDNN for accurate behavioral modeling and the linearization process of the power amplifier. An indirect learning process was selected to extract an inverse model of the power amplifier as well, using the same TDNN structure. The inverse TDNN model is directly used as a predistorter for the power amplifier. The linearization results with and without delay taps were compared and analyzed for a downlink WCDMA signal. The validity of the model structure and linearizer was proven by linearization testing, using a downlink CDMA2000 signal.
Hardware Set-up for the Measurements
To obtain the dynamic AM-to-AM and AM-to-PM characteristics of the power amplifier, the test set-up shown in Figure 1 was assembled using Agilent Technology’s Electronic Signal Generator (ESG) model E4438C, Vector Signal Analyzer (VSA) hardware/ software model 89641A and simulation software from Advanced Design Systems (ADS). A WCDMA signal was generated by the ESG and applied to the amplifier under test. After down-converting the output WCDMA signal of the power amplifier, the VSA collected the baseband I and Q signals. The dynamic baseband AM-to-AM and AM-to-PM characteristics can be identified by comparing the output I/Q signals with the input. The ADS digital package controlled the measurement system using GPIB and IEEE-1394 interfaces. The ESG provided an external trigger and reference signals to the VSA for synchronization.23 The final stage of the power amplifier was implemented to have 340 W-PEP, using a parallel combination of two push-pull amplifiers made of Freescale’s 170 W-PEP LDMOSFETs. Figure 2 shows a photograph of the amplifier final stage, including an isolator at the output and bias networks. An MRF9045, 45 W-PEP LDMOSFET drives the final stage. The overall amplifier chain has a power gain of 49 dB and a saturated output power of 54 dBm.
modeling of the power amplifier using tdnn
The configuration of the real valued TDNN was used and optimized as a modeling method for the power amplifier. Parts of the baseband input and output I and Q signals were used as the training data of the TDNN. Figure 3 shows the specific structure of the TDNN, which has an input layer, a hidden layer, an output layer and delay taps. The output I and Q signals can be expressed using the input I/Q signals, their previous signals having different time delays with multiple taps, and the activation functions. The output I and Q signals are formulated as
where φ1(x) and φ2(x) are the activation functions, which have the following functional representations in this experiment
The nonlinear characteristics of the power amplifier, that is AM-to-AM and AM-to-PM, were initially modeled using memory-less neural networks (without tapped delay lines). Subsequently, the tapped delay lines were added one by one to accurately model the nonlinear behavior of the power amplifier with memory effects. The training process adopts the well-known back-propagation algorithm, which minimizes the mean square error of the training data sets as the epochs increase. The number of delay taps for the I and Q signal paths were sequentially increased and the optimum number of taps was determined to be five. When the number of delay taps exceeds five, the modeling results improve only marginally despite a drastic increase in computational load. In similar fashion, five input neurons and two output neurons were selected in this experiment. The number of layers was optimized in the same way. Because the multi-layer structure did not exhibit much better performance than the simple single-layer structure, a very simple single-layer structure was chosen. Ten thousand samples of data were used for the training and 1000 epochs of simulation were conducted for one training event. After the training session, the model was tested with another 80,000 samples to see if the model predicts the nonlinear behavior of the amplifier well enough. The time-domain signals for the 80,000 measured samples and the predicted samples using the model are compared in Figure 4. Figure 5 also shows the dynamic AM-to-AM (a) and AM-to-PM (b) characteristics for the measured and predicted samples. An almost exact match between the measured and predicted data is demonstrated.
In particular, a significant scattering of the measured data due to memory effects can be seen, but the TDNN-based behavioral model tracks those variations well. The predicted power spectral density (PSD) matches well with the measured results, as shown in Figure 6. A slight mismatch in the spectral level could be observed, not because of inaccuracy of the model but because of a long-term memory effect possibly caused by a thermal accumulation or other environmental deviation during the measurements. Hence, the outstanding capability to model the nonlinear behavior of the power amplifiers in the presence of considerable memory effects is validated using the TDNN structure.
Predistortion Procedure with an Inverse TDNN Model
As with behavioral modeling, inverse training using a TDNN structure was performed to build a linearizer. The output I/Q signals of the power amplifier model, after extracting the linear gain of the amplifier, are used for the TDNN as the input I/Q data of the inverse model. The inverse TDNN model is also trained to minimize the mean square error between the output and the input data of the power amplifier. The well-trained neural network is copied to the front of the power amplifier in order to pre-distort the I/Q signals and eventually linearize the power amplifier. This procedure is called indirect learning.24 It is presented schematically in Figure 7. The overall modeling and linearization procedures are summarized in the flow chart shown in Figure 8. Using parts of the measured baseband I and Q signal samples, a neural network is initially set up with one hidden layer and no delay tap, and then a back propagation algorithm, abbreviated as BP in the flow chart, is run to extract the initial parameters of the model. After the initial run, one delay tap is added and the BP run again. This routine is repeated until very good modeling results are obtained or the number of iterations becomes more than an arbitrary constant k (five in these experiments). If the number of iterations becomes greater than k, the number of hidden layers is increased. The modeling routine ends and the linearization phase starts when a good modeling result is obtained; that is a good match between the measured and modeled data.
A very similar procedure is performed to optimize the inverse TDNN model as a predistorter, shown in the lower part of the chart. Five delay taps, five input neurons and two output neurons were used for the training, which is the same as with the power amplifier modeling. The training was continued for 1000 epochs. To validate the training process, 80,000 samples of the baseband I/Q signals were applied to the trained neural network. In order to verify the superior performance of the TDNN, the same indirect learning procedure was conducted with the conventional neural network without delay taps, which does not have the ability to compensate for nonlinearities associated with memory effects. PSDs using the neural network predistorters with and without delay taps are plotted and compared to each other in Figure 9. For a downlink WCDMA signal, more than 15 dB compensation is observed for the tapped delay neural network predistortion, while only 2 to 3 dB is observed for the neural network predistortion without delay tap. About 65 dBc of ACLR was achieved at 5 MHz offset. For a CDMA2000 signal, the improvements were approximately 20 dB and less than 10 dB, with and without tapped delay lines, respectively.
Conclusion
The power amplifier behavioral model, using an artificial tapped delay neural network, was built to effectively predict the complex nonlinear behavior of the power amplifier in the presence of strong memory effects. Using this behavioral model and modeling technique, a digital predistortion linearizer, using an indirect learning process, was developed and tested in order to linearize the 3GPP base station power amplifiers. Overall procedures of modeling and linearization were efficiently organized and described. The systematic flow of linearization, including behavioral modeling, model verification and building of a predistorter using an indirect learning process, were developed. Compared with the linearizer using a conventional neural network, the TDNN-based linearizer showed better results, due to its ability to handle memory effects. When the TDNN predistorter was used, more than 15 dB compensation was obtained for a downlink WCDMA signal. Otherwise, for the predistorter without tapped delay, merely 2 to 3 dB improvements were observed, which verifies that the TDNN predistorter has an excellent performance on the linearization of the high power amplifiers for 3GPP systems and that memory effect compensation is very important for modeling and linearization of power amplifiers.
Acknowledgments
The authors would like to thank professors Shawn P. Stapleton and Wan-Jong Kim, both of Simon Fraser University in Vancouver, Canada, for their great support in test-bed set-up and manipulation. This work was supported by grant No. RTI04-03-04 from the Regional Technology Innovation Program of the Ministry of Commerce, Industry and Energy (MOCIE).
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Hoon Hwangbo received his MS degree in electrical and computer engineering from Sungkyunkwan University, South Korea, in 2001, where he is currently working toward his PhD degree. His research interests include RF power amplifiers, memory effects, microwave packaging and signal integrity.
Sung-Chan Jung received his BS degree in electronic engineering from Sungkyunkwan University, South Korea, in 1998, where he is currently working toward his PhD degree. His current research interests include RF power amplifiers, linearization techniques and efficiency enhancement techniques.
Youngoo Yang received his PhD degree in electrical and electronic engineering from Pohang University of Science and Technology (Postech), Pohang, South Korea, in 2002. From 2002 to 2005, he worked for Skyworks Solutions Inc., Newbury Park, CA, where he designed power amplifiers for various cellular handsets. Since March 2005, he has been with the school of information and communications, Sungkyunkwan University, Suwon, South Korea, where he is currently an assistant professor. His research interests include the design of power amplifiers, RF transmitter / receiver sub-systems, RFIC design and modeling of high power amplifiers or devices.
Cheon-Seok Park received his BS degree in electrical engineering from Seoul National University and his PhD degree in electrical and electronic engineering from the Korea Advanced Institute of Science and Technology (KAIST), South Korea, in 1988 and 1995, respectively. He has been a professor in the school of information and communications at Sungkyunkwan University, South Korea, since 1995. His research interests include RF power amplifiers, linearization techniques and efficiency enhancement techniques.
Byung-Sung Kim received his PhD degree in electronic engineering from Seoul National University, South Korea, in 1997. He joined the school of information and communications at Sungkyunkwan University, South Korea, in 1997, where he is currently an associate professor. His research interests include RFIC design.
Wansoo Nah received his PhD degree in electrical engineering from Seoul National University, South Korea, in 1991. He then joined the Korea Electrical Research Institute (KERI) as a senior researcher and was also a guest researcher in the Superconducting Super Collider Laboratory (US) for two years. He has been a professor in the school of information and communications engineering at Sungkyunkwan University, South Korea, since 1995. His present areas of interest include signal integrity, emi/emc and RF power amplifiers.
