Extrinsic Layer
This layer incorporates parasitics from the gate and drain manifold, as well as the gate-drain fringing capacitances from the coupling of the gate and drain fingers. This includes the access resistances as well as the inductance and capacitance of the metal lines contacting the gate and drain that act as a transmission line at RF frequencies and beyond. The manifolds for the gate and drain introduce an additional inductive and capacitive effect that is considered.
GAN MODELING PERFORMANCE
Small-Signal Model Accuracy
An accurate small-signal model is important to properly design the matching networks and perform stability analysis. The dynamic nature of GaN devices with trapping and self-heating causes unique changes to the small-signal parameters. The slope of the I-V curve is greatly affected with a changing drain-source voltage (Vds). This can be seen in Figure 4, where the I-V curve is shown at different biases (Vds). This highlights the saturation current (vertical axis) and threshold voltage (horizontal axis).
As shown in every graph, there is an apparent change in the threshold voltage (Vth) when the quiescent bias is increased. Vth becomes positive until the quiescent bias point; however, this does not go on indefinitely (see Figure 5a). Vth becomes positive at 15 V and stays constant beyond 15 V. This apparent shift in the Vth must be incorporated in the small-signal model. Wolfspeed models take care of the additional adjustments in the formulation.2
Figure 5 Small-signal model evaluation for the G40v4 node, checking for S-parameter and gain scaling vs. bias and size.
The Wolfspeed model is evaluated for its scaling robustness across a wide range of biases and sizes to ensure model accuracy. This can be seen in Figure 5, where the model is validated with various gate fingers, gate widths and bias conditions to provide usage guidelines. Every quarter, six to 12 wafers are submitted for each GaN process technology node to ensure that the nonlinear model continues to accurately reflect the devices. The measured results very closely match the model simulations, ensuring an accurate small-signal model for designers over a wide range of gate widths, above the knee voltage and below the knee frequency.
Large-Signal Model Accuracy
Large-signal load-pull, source pull and power drive-up are also verified for various frequencies, bias conditions and device sizes to ensure accurate large-signal scaling and drive-up predictions (see Figure 6). The power contours in the load-pull analysis are critical not only to observe the impedance but also to readily observe the shape to ensure that the device’s large-signal output capacitance or output current and output voltage characteristics are within specifications.
Figure 6 Large-signal simulation vs. model for the V3-V4 nodes: load and source-pull (a) and gain and efficiency vs. power (b).
This is especially important near the impedance region in which a designer will work to create a wideband PA. The power drive-up curves are useful for overall model validation in the back-off and compression regions. With an accurate and scalable large-signal model in place, it is possible to design much larger power transistors. When working with large-signal models, designers must ensure that they do not drive the model deeply into compression where voltage and current clipping, or breakdown, occurs as the model will not predict this accurately. These parameters are difficult to control, even for measured results.
Model Verification: MMIC and PCB Levels
Validating the model at the transistor level may not show the bigger picture. Major issues can crop up at the circuit level, where the extrinsic portion of the nonlinear model doesn’t necessarily correspond with reality. Wolfspeed validates models at the circuit level by dropping the nonlinear model into larger MMIC and printed circuit board (PCB) circuit designs. Model realism is further validated by comparing model results with measured results. The process involves observing the magnitude of key parameters such as output power (Pout), PAE and gain (|S21|) for wideband circuits and discerning whether the model results track with the measured results (see Figure 7).
Figure 7 MMIC PA design (a) with simulated vs. measured performance (b).
Figure 8 Discrete product measured vs. simulated performance with updated nonlinear model.
Wolfspeed leverages discrete products to visualize modeled and measured S-parameter results at the PCB and package level. Figure 8 shows small-signal S-parameters (|S11|, |S22| and |S21|) as well as large-signal Pout, PAE and gain parameters for old models, updated newer models and measured results. The old models are included to readily note any discrepancies that would make apparent any issues with an updated nonlinear model.
NONLINEAR DEVICE MODEL WITH THE WOLFSPEED GAN PDK
Working with the nonlinear device model using the Wolfspeed GaN PDK involves 13 model parameters that depend upon device geometry, thermal characteristics, yield-analysis parameters, model-related parameters, manifold characteristics and via configuration (see Figure 9).
Figure 9 Nonlinear device model in Wolfspeed’s GaN PDK.
Geometrical parameters include the scaling size, number of parallel FETs, gate fingers, gate-source pitch and gate-drain pitch, while thermal parameters include base temperature and thermal resistance. Yield-analysis parameters consider process variations that might change intrinsic model parameters such as Cgs and transconductance. Designers can either use the manifold parameters set by the model or design their own manifold metallization structure and simulate it using an electromagnetic simulator to obtain an S-parameter model to use in a large-signal model after de-embedding.
Typical Design Process
The general amplifier design process is to first load-pull the transistor model within a harmonic balance simulator in which the designer must ensure that the transistor does not become unstable in the unmatched environment. If this happens, the source and load-pull will give inaccurate results or simply not converge. These source and load impedances are the foundation for the initial circuit design.
After this, the completed amplifier can be simulated and optimized. Finally, amplifier layout can occur with all required electromagnetic blocks. These designs rest heavily on the accuracy and scalability of their small-signal and large-signal models wherein the measured results should be well-correlated with the model results.
GaN Design Considerations
The following is especially true for GaN HEMTs. The dynamic trapping behaviors impact the accuracy of both small-signal and large-signal models. GaN also has a relatively soft compression characteristic under class (ABCF)B to class (ABCF) operation. This shifts the traditional design methodology in which the typical specifications for compression and linearity (i.e., P1dB, P3dB) are not actually relevant for GaN devices. Instead, GaN HEMTs show better efficiency and linearity to higher compression levels than other semiconductor technologies.
Early compression in driver stages of multi-stage amplifiers needs to be considered and accounted for in sizing of drive ratios, as gain may be reduced earlier in the power drive-up curve. GaN HEMTs also tend to have gain expansion near the pinch-off bias condition. To improve linearity, it may be preferable bias the amplifier near class (ABCF)B, where a sweet spot can be found between expansion and soft compression.
CONCLUSION
GaN HEMT devices are highly sought-after devices in the A&D industry due to their high efficiency, high gain and straightforward matching characteristics. To take full advantage of these devices, however, designers must rely heavily on the accuracy of their device models. With good device models, designers can exploit the full device potential and perform more in-depth, what-if analyses for faster design cycles and greater first-pass design success.
This extends to multi-amplifier design architectures where repeatable performance is relied upon for an accurate statistical analysis with real-world component variations and fabrication tolerances. The merit of these nonlinear models for a GaN design as well as the ones provided with Wolfspeed’s packaged designs offer massive gains in modeling flow efficiency.
References
- “6-Port GaN HEMT Models Help Designers Optimize PA Efficiency,” Reprint from IEEE Transactions on Microwave Theory and Techniques, Vol. 15, Issue 6, 2014, Web: https://assets.wolfspeed.com/uploads/2020/12/133_6Port_GaN_HEMT_Models_Help_Designers_Optimize_PA_Efficiency.pdf.
- Y. Liu, “Wolfspeed RF Device Modeling,” Web: https://resources.system-analysis.cadence.com/rf-microwave/wolfspeed-rf-device-modeling.
