Smartphone antenna impedance and aperture variation due to external elements, such as the position of the user’s hand, have been widely studied, leading to the use of antenna tuners (AT) in the RFFE to dynamically compensate such variation. ATs are implemented as close to the antennas as possible and are the first RFFE elements that must withstand large VSWR. Depending on the design, ATs may require the RF-SOI substrate BOX to withstand voltages greater than 100 V. Some RFeSI substrates offer BOX soft breakdowns greater than 150 V by tuning the BOX layer thickness appropriately (see Table 1).

When comparing RF, mmWave and integration capabilities, Figures 1 and 2 show a clear advantage of TR SOI over HR-SOI. TR RF-SOI has greatly contributed to the success of CMOS in RF and mmWave front-ends. As RFFEs evolve, TR SOI substrates must also evolve to address more stringent requirements. Higher frequency measurements, substrate modeling and material developments are being pursued for future applications, and these are described in the following sections.

MMWAVE CHARACTERIZATION

Signal attenuation in transmission lines, particularly CPW lines, is strongly affected by the free carriers in the underlying substrate. The total propagation loss, which comprises metallic losses in the lines as well as losses from the substrate, is often used to compare the RF performance of different substrates. Figure 3 plots the propagation loss (α) versus frequency of CPW lines on different silicon substrates, showing the separate contributions from the metallic and substrate losses. For a 50 Ω transmission line, α is equivalent to the IL per unit length.

Figure 3 Measured insertion loss on HR-SOI and RFeSI90 substrates (a) compared to simulated HR-SOI substrate model (b).

CPW lines with different lengths (i.e., 426, 906, 2106, 2526, 2826 μm) and the same cross section were measured and the multiline thru-reflect-line (mTRL) algorithm applied to extract the propagation constant.⁸ The mTRL algorithm with redundant line measurements increases the extraction accuracy by reducing the measurement noise, which is inherently larger at mmWave frequencies. The separation of the metallic and substrate losses was obtained using a procedure described by L. Nyssens et al.⁹, which is valid at mmWave frequencies.

The different samples were manufactured with the same CPW pattern, such that they have similar metallic losses versus frequency. The increasing IL with frequency is caused by the skin effect, a metallic loss mechanism. The introduction of HR silicon improved the IL by reducing the number of free carriers in the handle substrate. Nevertheless, the presence of the PSC at the oxide-silicon interface degrades the IL. This is suppressed when a TR layer is used, as with the RFeSI90 wafer. Therefore, the TR SOI substrates combining a HR handle silicon substrate and TR layer have negligible substrate-related losses. At sufficiently high frequencies, when the slow-wave mode is suppressed - above a few tens of MHz for TR substrates and above 10 to 20 GHz for HR substrates - the substrate losses are frequency independent and agree with the substrate model. The improvement in IL for the RFeSI substrates is valid across the entire mmWave frequency range.

SIMULATING RF-SOI SUBSTRATES

Figure 4 Measured vs. simulated second harmonic power.

Figure 5 Measured vs. simulated second harmonic power of two modified trap-rich wafers and the reference RFeSI80 sample.

Developing engineered materials for advanced applications is a complex, time- and resource-consuming process, which is more efficient with calibrated simulation. Accurate small-signal modeling has been developed using a combination of electromagnetic (EM) and technology computer-aided design (TCAD) tools to account for the lossy nature of the silicon substrates and conductive interfaces.^10,11 While simulating a semiconductor substrate’s large-signal behavior is more of a challenge, the authors have developed the capability to link material properties to RF performance. To model the distortion induced by the substrate on a CPW line’s signal, modeling is based on simplified EM propagation models which are complementary to solving the semiconductor transport equations and trapping phenomena in a transient, large-signal, time-domain TCAD approach. The model has been validated with several HR and TR samples having key differences in material parameters, enabling the relative importance of such differences on the linearity of the RF substrates to be assessed.

Figure 4 shows the second harmonic power levels versus DC bias for three substrates, comparing measured and modeled performance. The DC bias induces a mirror charge below the BOX. An RFeSI80 TR wafer is shown for reference; the other two wafers are HR, each with a different BOX material: the first oxide, the second alumina (Al2O3). Oxide-silicon interfaces are known to have a positive, fixed interfacial charge density, reflecting the creation of an electron PSC,1,3 while the charge density is negative at alumina-silicon interfaces, reflecting creation of a hole PSC. The interfacial fixed charge densities of the HR Oxide and HR Al2O3 samples were extracted from low frequency CV measurements of classical MOS capacitor devices at 8 x 10¹¹ and ‐6 x 10¹¹ cm^‐2, respectively (not shown), and the same values were used in the model. The model correlates well with the measured data, accurately capturing the strong dependence on bias voltage and fixed charge.

By introducing trap energy states in the polysilicon TR layer, modeling predicts the increase in effective resistivity, as well as the decrease in power of the generated harmonic. Figure 5 plots the second harmonic versus fundamental output power for three RFeSI substrates, comparing measured and modeled performance. One primary material parameter difference distinguishes each substrate from the others, and the model captures the relative impact of each parameter on the harmonics generated by that substrate. As a reference, the RFeSI80 substrate was modeled and measured. Using a more resistive polysilicon layer and handle wafer, an RFeSI100 was fabricated and modeled. Tailoring the resistivity in the model is almost sufficient to justify the 20 dB difference in the second harmonic power levels between these two substrates. Finally, the RFeSI80, introduced significant Boron contamination within the polysilicon layer, confirmed by SIMS and SRP data (not shown). Boron degrades the substrate impedance and raises the harmonic levels; adding the Boron profile into the model generates accurate estimates of harmonic performance.

This physical modeling gives key insights into the effect of the fundamental material parameters on RF loss and linearity performance and is a useful tool when designing substrates to meet given RF specifications.

BETTER PERFORMANCE AND TEMPERATURE STABILITY

RF-SOI substrates need to evolve to support new and more stringent RF requirements. Today, RFFE linearity is often not limited by the substrate, yet a large field of RF applications would benefit from RF-SOI substrates with better HD and IMD specifications. RFeSI linearity may be enhanced by improving the handle wafer resistivity and polycrystalline silicon trapping efficiency (see RFeSI100 in Figure 1). However, there are limits to the resistivity level that can be achieved with bulk silicon while guaranteeing stability, mechanical strength and affordability.

Figure 6 RFeSI second harmonic power vs. temperature.

Figure 7 Second harmonic vs. ε for porosification setups yielding steep and shallow trade-offs.

Other limitations of HR silicon are its relatively small bandgap and high dielectric constant. A 1.1 eV bandgap implies that the number of intrinsic carriers in the bulk silicon, which increases with temperature, becomes higher than the residual wafer doping in the range from 50°C to 90°C. Above this temperature, the resistivity and associated RF performance start degrading (see Figure 6). While this is not an issue for most applications, some require performance stability to 150°C, such as grade 1 and 2 automotive. These applications require materials with resistivity independent of temperature.

Soitec has built SOI wafers with a porous silicon layer, which can be viewed as thin silicon membranes separated by gaps. It presents a huge surface area, on the order of 500 m²/cm³, so the many dangling bonds and surface states act as traps. Because the silicon membranes are so thin, all carriers are within trapping distance of the surface and are also subject to coulomb scattering. This ensures a low free carrier concentration and mobility, even when the temperature rises. The benefits of porous silicon for RF applications are well known, with demonstrated temperature stability on relatively thick layers, usually greater than 50 μm.^12,13

Using SOI wafers and a thin buried porous silicon layer, to our knowledge, Soitec is the first to demonstrate very low HD levels and complete independence versus temperature up to 200°C, as shown in Figure 6. This performance has an added benefit: because porous silicon is essentially a composite material of silicon and empty spaces, its permittivity is lower than the usual 11.7. Thus, the transmitted signal sees a material with a reduced effective permittivity, which benefits HD, IL and signal isolation.

The effective RF performance and permittivity of porous silicon layers is dependent on the porosification process and material properties, such as porosity level, structure type, pore size, surface state and thickness. This is illustrated in Figure 7, which shows second harmonic power versus permittivity when different trade-off configurations are used to fabricate the porous silicon layer. The figure shows obtaining adequate performance, temperature stability and low permittivity requires the proper fabrication process.

CONCLUSION

This article illustrates how substrate engineering brings additional linearity and value for RF and mmWave applications. Measurement setup and extraction procedures enable evaluating the substrate performance through representative metrics. With a physical understanding of material properties, the EM behavior of the substrates can be accurately modeled, reproducing the effects of material parameters on HD. Leveraging these developments enables a path to better linearity, temperature-independent properties and tuned permittivity, which can be implemented in new engineered substrates to meet even higher performance requirements and the needs of future applications.

References

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