A 3 V Small Chip Size GSM HBT Power MMIC with 56 Percent PAE

TECHNICAL FEATURE

A 3 V Small Chip Size GSM HBT Power MMIC with 56 Percent PAE

This article describes a three-stage 56 percent power added efficiency (PAE) InGaP/GaAs hetero-junction bipolar transistor (HBT) power MMIC for use in Global System for Mobile Communications (GSM) applications at 900 MHz. An output power of 2.7 W is obtained at the connectors of an evaluation board with a single supply voltage of 3.2 V. The large-signal gain is in excess of 32 dB, and the dynamic range for power control exceeds 80 dB. The chip size of only 2 mm² allows housing in a thin shrunk small outline package (TSSOP10), which occupies less than one half of the board area compared to the packaged GSM devices used previously. The design is performed in two steps. First, reasonable conditions for output power can be obtained by on-wafer load-pull measurements, which, in conjunction with appropriate small-signal simulations, are used to establish the basic circuit topology. Second, further performance improvements are achieved by large-signal simulations.

J.E. Mueller, U. Gerlach,
G.L. Madonna, M. Pfost,
R. Schultheis and P. Zwicknagl
Infineon Technologies
Munich, Germany

Power amplifiers are key parts in handheld telephones, having a significant impact on important system parameters such as talktime, size and overall cost. GaAs MESFETs offer acceptable 3V performance with low chip cost. However, they normally require two supply voltages (both positive and negative) and a drain supply switch for low drain currents in a standby mode. The additional circuitry increases cost and board area. These disadvantages are circumvented by devices such as Si laterally diffused metal-oxide semiconductor (LDMOS), Si bipolar and GaAs HBTs, which allow unipolar operation. However, the drawback of Si technologies is that for the application in mind a power device is required which combines good large-signal performance at low voltage operation as well as high breakdown voltages. (Amplitudes of up to 15 V may occur at the amplifier output if the phone is used when charging the batteries.)

GaAs HBTs offer an attractive solution to this problem as they achieve excellent high frequency performance combined with a high breakdown voltage. This characteristic holds even for a relaxed 3 µm lithography due to the high mobility and carrier velocity in GaAs. In addition, the use of GaAs offers low parasitics due to the semi-insulating substrate. Thus, high-Q passive elements (metal-insulator-metal (MIM) capacitors, inductors and transmission lines) are available for matching. Moreover, substrate vias to the backside can be processed, allowing low inductance ground connections, small chip sizes and use of small packages (such as TSSOP10) with low lead count.

DEVICE PROCESSING

The HBT power MMICs were fabricated using an in-house 4" wafer production line for GaAs MESFETs, due to the high degree of compatibility of both processes. Four-inch-diameter metal organic chemical vapor deposition (MOCVD) grown wafers were processed using i-line stepper photolithography and a non-self-aligned method. The epitaxial layer sequence consists mainly of a n-doped InGaP (4 * 10¹⁷ cm^­3 ) emitter layer, a uniformly doped p-GaAs (4 * 10¹⁹ cm^­3 ) base layer, a 700 nm n-GaAs (2 * 10¹⁶ cm^­3 ) collector and a n-GaAs (5 * 10¹⁸ cm^­3 ) subcollector layer of the same thickness. Dopants for the n- and p-type layers are Si and C, respectively. Other important features of the HBT process are non-alloyed metallizations for emitter (WSi/Ti/Pt/Au) and base (Pt/Ti/Pt/Au) contact formation; selective etch stops for dry etching to improve process control and device homogeneity across the wafer; and MIM capacitors, electroplated airbridge metallization, wafer thinning and substrate vias to the backside.

The multi-emitter cells are composed of up to 60 3.2 * 45 µm² emitter fingers with 32 µm spacing, resulting in a compact power cell design. Thick emitter airbridges serve as a thermal shunt^1,2 by spreading the heat over the chip. In addition, they contribute to a more uniform distribution of the temperature between different emitter fingers.

The optimum characteristics of the HBT process are summarized in Table 1. High values for the transit frequency f_t and maximum frequency f_max of 30 and 60 GHz, respectively, are obtained in conjunction with low values for both on-resistance and offset voltage. Thus, high values of output power and efficiency can be achieved readily with comparatively low supply voltages in the wireless frequency bands. Note that the collector-emitter breakdown voltage with open-base exceeds 15 V and is therefore suitable for application in handheld telephones.

HBT MODELING

The design of RF power circuits clearly requires accurate transistor models. For this reason, a large-signal GaAs HBT model has been developed based on the well established approaches used for Si bipolar transistors.³ The circuit topology is shown in Figure 1. This large-signal model allows the complete electrical description of HBTs not only for DC and small-signal RF behavior, but also for nonlinear effects such as gain compression, intermodulation distortion and thermally induced current collapse.

During development of the model it was noted that in power applications, the transistor junction temperature often differs significantly from the ambient temperature due to the high dissipated power in conjunction with the low thermal conductivity of GaAs (more than three times lower than Si, at room temperature).

In contrast to the standard Spice-Gummel-Poon model, self-heating cannot be neglected and is therefore correctly taken into account in this model.⁴ As a result, an additional thermal circuit is used, which consists of a current source to model the dissipated power P_diss , a thermal resistance R_th and a thermal capacitance C_th . Thus, the voltage drop along R_th is equal to the junction temperature increase ΔT over the ambient temperature. A special on-wafer measurement technique has been developed to determine R_th ,⁵ while C_th can be extracted from pulsed measurements. In addition, numerical temperature simulations proved to be very helpful to determine and optimize the thermal behavior especially of large transistor cells.

The model was thoroughly verified by comparison to experimental results. As an example, Figure 2 shows the measured and modeled output characteristics of an HBT. An excellent match between the corresponding curves can be observed, even when considering the negative slope of the output characteristics, which is typical for GaAs HBTs and caused by self-heating. In this case, the junction temperature extends from the ambient temperature of 20°C up to 130°C, demonstrating that the model is valid over a large temperature range.

In addition, the model was experimentally verified for its RF behavior, both in small- and large-signal conditions. Excellent agreement between measured and modeled S-parameters was obtained for a typical GSM power amplifier operating point (V_CE = 3 V and J_C = 0.2 mA/µm² ) up to 20 GHz, as demonstrated in Figure 3. Furthermore, f_t can be predicted with high accuracy for forward Gummel plot conditions (V_BC = 0) and different ambient temperatures from ­40° to 110° C, as shown in Figure 4. The large-signal simulation of a power transistor cell also agrees very well with the measurements, as discussed in more detail in the following sections.

ON-WAFER CHARACTERIZATION OF LARGE EMITTER AREA POWER HBTS

DC, Pulsed and Small-signal RF Behavior

For evaluation of the performance of large emitter area power transistors, on-wafer large-signal measurement techniques have been developed, which include static IV output characteristics for currents up to 5A, pulsed IV output characteristics for currents up to 10A, static and pulsed S-parameter measurements in those current ranges, as well as active harmonic load-pull⁶ measurements up to 10 W. Thus, after finishing front-side processing, the quality of the wafers with respect to their power performance can be judged, which helps to increase process optimization.

Figure 5 shows pulsed IV measurements of the output characteristics (collector current I_C up to 4 A) of transistors with emitter areas of 1440, 4320 and 8640 µm² . (The circle represents the operating point with the maximum specified collector current.) The collector current of the 1440 and 4320 µm² transistors was multiplied by a factor of six and two, respectively, to compare their performance with the largest cell. The pulse conditions were chosen according to GSM requirements (T_on = 0.58 ms). It can be observed that the currents of the large HBTs scale accurately with their emitter area. This demonstrates that the HBT process and layout have been successfully optimized.

The on-wafer measured maximum available gain (MAG) (or the maximum stable gain (MSG), if the transistor is not unconditionally stable) as a function of frequency for several HBTs with an emitter area of 4320 µm² (V_CE = 3.2 V, I_C = 432 mA) is represented in Figure 6. MSG values in excess of 25 dB have been obtained at 900 MHz. The plots refer to ten HBTs selected from different locations across the same wafer. The small dispersion of the characteristics demonstrate good homogeneity of RF-gain across the wafer for the large emitter area power HBTs.

Large-signal RF Operation

The results presented in the following sections were obtained for an HBT with 4320 µm² emitter area, under single-tone, 900 MHz excitation. The transistor was chosen to operate in near-class B, by a proper choice of the bias conditions. In class B mode, the DC collector current swings from a small quiescent value I_CQ (in absence of RF signal) to the normal operating point (I_C,max ), while the RF input power level is increased, since the RF signal is rectified by the base-emitter diode as shown in the device model. This effect is usually referred to as self-biasing.

A simplified picture of the situation is presented in Figure 7. The swing of the instantaneous base current and voltage is shown for two different RF power levels, together with the exponential base-emitter-diode characteristic and the DC load line (with slope 1/R_B ). As the RF power increases, the mean value of the base current moves from I_B1 to I_B2 . In a similar way, the swings of the instantaneous collector current i_C and voltage v_CE for increasing RF power levels are shown. (For simplicity, the RF load impedance Z_L is considered purely resistive.) Due to self-biasing, the DC component of the collector current increases from I_C1 to I_C2 . The amount of this self-biasing effect depends, in the first instance, on the base bias voltage V_BB , the bias resistor R_B and the RF load impedance Z_L .

The advantage of class B operation -- with respect to class A -- is a considerable improvement in power added efficiency (PAE) over a wide dynamic range, as the bias current is automatically adjusted according to the RF signal level. On the other hand, the HBT behaves intrinsically as a nonlinear device, and the performance of the amplifier in terms of signal distortion is somewhat compromised, even for small RF power levels. The main nonlinear effect is a considerable change in both gain and phase of the HBT transfer characteristics for higher RF levels, corresponding to AM-to-AM and AM-to-PM conversion phenomena. Nevertheless, GSM applications involve only constant envelope modulation so that the transistor can be pushed even into hard saturation (where high efficiency is obtained), provided that the necessary harmonic suppression is guaranteed to meet the electro-magnetic compatibility (EMC) specifications.

Figure 8 shows the output power P_out , PAE and DC collector current I_C as a function of the input power P_in . The measured characteristics are compared to the simulation results obtained with the large-signal model previously described. The load impedance Z_L (f₀ ) at the fundamental frequency (f₀ = 0.9 GHz) was adjusted to give a good compromise in terms of output power P_out (in excess of 31.5 dBm) and efficiency (56 percent). Note that the DC collector current increases from I_CQ = 50 mA to more than 750 mA at maximum output power. The operating gain shows values in excess of 17.5 dB. Note that this value is appoximately 7 dB less than the maximum available gain shown previously. There are two reasons for this: First, the optimum load impedance for maximum gain is generally different from the one for maximum output power. Second, the quiescent current I_CQ is one order of magnitude lower than the bias current used in the small-signal measurements.

Due to the inherently nonlinear nature of the self-biasing effect, RF harmonics play an important role in defining the transistor behavior. Figure 9 shows the harmonic content of the RF output signal as a function of the input power. The output power P_out (i=f₀ ), i = 1, ... ,5, is defined as the net power delivered to the load impedance Z_L =f₀ ) at the frequency i=f₀ . The results shown were obtained with the fundamental load Z_L (f₀ ) adjusted for maximum output power and the harmonic impedances Z_L (i=f₀ ), i = 2,...,5, set to 50 Ω.

Even for low input powers, the level of the harmonics is relatively high, due to the low quiescent current and to the exponential I-V characteristic of the base-emitter diode (see device model). As the RF signal level increases, the output swings more and more in the I-V plane, until waveform clipping occurs at low V_CE voltages or, if the load line is steeper, when current gain compression occurs. In both cases, a second nonlinear effect arises in addition to the base-emitter diode distortion. The collector current waveforms for two different RF power levels are shown in a previous figure. From their Fourier analysis, it has been noted that the distortion due to output clipping gives rise to spectral components that, with respect to the base-emitter diode contribution, are mainly opposite in phase for even harmonics and mainly in phase for odd harmonics. As a result, the level of the second harmonic shows a minimum at the beginning of the output power saturation (due to partial cancellation of the two non-linear contributions) along with a noticeable increase in the third harmonic content.

These considerations lead to the following conclusions. First, the relevance of the harmonic content in class B operation suggests that the harmonic impedances Z_L (i=f₀ ) should not be left uncontrolled, since they can play an important role in determining the performance of the amplifier. Second, the optimum load impedances may depend considerably on the operating conditions (that is, in this case, on the RF signal level).

Therefore, the PAE dependence on the second harmonic load Z_L (2=f₀ ) -- that is, on the reflection coefficient Γ_L (2=f₀ ) -- was first studied. The main results are shown in Figure 10. The optimum loading conditions were observed to be purely reactive (|Γ_L (2=f₀ )| = 1), so that the harmonic termination did not dissipate any power. Therefore, the efficiency is reported as a function of the phase of the reflection coefficient Γ_L (2=f₀ ) only. Four PAE curves are plotted for the different P_in levels shown in the plot of P_out vs. P_in .

At RF power levels lower than the 1 dB-compression point (case a and b), the optimum load is close to a short circuit ( Γ_L (2=f₀ ) = 180°). Moreover, the difference between the minimum and maximum PAE values is significant (for example, in case b the efficiency ranges from 40 percent to 49 percent). On the other hand, if the transistor is driven into hard saturation (case d), the PAE span is similar, but now the best loading condition for the second harmonic is close to an open circuit ( Γ_L (2=f₀ ) = 0). This can reasonably be explained by a change in the sign of the second harmonic, confirming the assumption that -- at higher power levels -- the nonlinearity from output waveform clipping has a larger impact than the contribution of the base-emitter diode. However, normal operating conditions for GSM applications are more like case c, where the gain compression is between 1 and 3 dB and the second harmonic level shows a minimum. As expected, in this case tuning the second harmonic impedance has only a small impact (PAE ranges between 52.0 percent and 55.5 percent), and the major role is played by the termination of the third harmonic.

As an example, Figure 11 shows constant PAE contours on the Γ_L (3=f₀ ) plane, with the input power adjusted for 3dB gain compression. The load impedance Z_L (f₀ ) at the fundamental frequency is adjusted for optimum power output and efficiency. The second, fourth and fifth harmonics were terminated by a 50 Ω load. The optimum third harmonic load was found to be slightly capacitive and close to a short. Compared to the 50 Ω case, the PAE increases from from 56 percent to 61 percent, and P_out from 31.5 to 31.8 dBm. Further tuning of the fundamental load has shown no significant improvement of output power and PAE.

In conclusion, there is a simple and intuitive way to determine which of the harmonics should be tuned, and if the effort of tuning more than one harmonic is justified. For those decisions, the spectral harmonic content for the device has to be considered at the large-signal conditions of interest (that is, at the required power level, with optimum load at fundamental and all harmonic impedances equal to 50 Ω). As a rule of thumb -- confirmed by experiments -- if the power of one harmonic exceeds the others more than 6 dB, then it is not worthwhile to tune harmonics other than the largest one.

CIRCUIT DESIGN AND MMIC RESULTS

The targeted output power for the GSM MMIC in a 50 Ω environment was 34 dBm at 3.2 V for an input power of 3 dBm. From these specifications, a required linear gain of at least 35 dB can be estimated. Additional design targets were an isolation of at least 70 dB at P_in = 3 dBm when the MMIC is set to its off-state, an analog power control of at least 50 dB by varying a control voltage, second harmonic suppression of at least ­40 dBc and packaging in TSSOP10 with heatsink.

The design was performed in two steps. First, the results of load-pull measurements and small-signal simulations were used. The size of the emitter areas required for the various amplifier stages were determined from on-wafer load-pull data of 0.5 W HBTs, which were available at the time of the design. Based on this information, small-signal simulations were carried out to fix the basic circuit topology and ensure adequate small-signal characteristics. The gain as well as the isolation targets required three amplifier stages, as shown in Figure 12. The emitter areas for the transistors in the first, second and third stages were scaled with a factor 1 : 7 : 49. (From gain considerations, other factors could be chosen. However, this is critical due to device tolerances and design inaccuracies, as the risk increases that one of the driver stages goes into saturation before the final stage.) The load impedances required for the various stages were estimated from the load-pull data and adequate interstage networks designed. The DC blocking capacitors, as well as the bond and packaging parasitics, were implemented in the interstage network designs. Circuit stability was ensured by small resistors at the base and RC-feedback networks between collector and base of each stage. All those network designs were done using the large-signal HBT model only for small-signal simulations until the required small-signal performance had been obtained. Finally, in a second step of the design cycle, further optimizations of the circuit performance were achieved by fine-tuning critical elements based on the results of large-signal simulations with the electrothermal HBT model.

The power performance of the MMIC was investigated using an evaluation board where the external fundamental load matching circuit (Z2, C4) was adjusted for optimum output power and efficiency. The capacitor C3 (including its inductive parasitics) was used for harmonic tuning. Its value was chosen so that a near-optimum condition for the third harmonic termination was achieved for high PAE (as described in the previous section), while at the same time the second harmonic is almost shorted for good suppression. This solution keeps the harmonic tuning circuit very simple (at a small price in terms of output power and PAE, however).

Figure 13 shows output power and PAE of the amplifier measured at the connectors of the evaluation board as a function of the power control voltage. An output power of 2.7 W is achieved with a single supply voltage of 3.2 V. The maximum large-signal gain is in excess of 32 dB, and the dynamic range for power control exceeds 80 dB. Note that this excellent performance is achieved in a small package (TSSOP10), which occupies less than one half of the board area compared to the packaged GSM devices used previously.

CONCLUSION

A small chip size InGaP/GaAs HBT MMIC power amplifier housed in a TSSOP10 package has been developed for low voltage wireless applications. On an evaluation board, the GSM MMIC achieved a P_out of 2.7 W and 56 percent PAE at 3 dBm input power and a single supply voltage of only 3.2 V. For the design, on-wafer measurements of large-emitter area power HBTs, as well as an accurate electrothermal HBT large-signal model, have been successfully used. In addition, on-wafer load-pull measurements provided new insight concerning the influence of harmonic load terminations. A simple method was discussed to decide which of the harmonics should be tuned, and whether the effort of tuning more than one harmonic is justified.

ACKNOWLEDGMENT

Part of this work was supported by the German Federal Ministry for Education, Science, Research and Technology under contracts no. 01BM613/8 and 01BM614/9. This article is based on material first presented at the European Microwave Conference held in Paris, October 2000. *

References

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