Pentek Inc. introduced intellectual property (IP) support for the VITA 49.2 data transport protocol in the Pentek Navigator™ Design Suite. The Jade™ Model 71141(1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch 6.4 GHz D/A) and Model 71851 (2-Ch 500 MHz A/D with DDC & 2-Ch 800 MHz D/A with DUC) data converter XMC modules, based on the Xilinx Kintex Ultrascale FPGA, are the first products available with the new IP modules.

The ANSI/VITA 49.2 standard, which is part of the VITA Radio Transport (VRT) family of standards, defines a signal/spectrum data transport protocol that expresses spectrum observation, spectrum operations and capabilities of RF devices. VITA 49.2 is used for conveying digitized signal information among signal acquisition/generation and processing elements in a communication, radar or similar system. The Model 71141 and Model 71851 implement the VITA 49 packet format for the ADC/DDC data being moved to host memory via DMA transfers.

Standard elements in the VITA 49.2 packet include: Signal Data Packet Type, Stream Identifier, Integer Seconds Timestamp, Fractions Seconds Timestamp and Trailer.  Optional programmable elements that can be added to a packet include: Packet Size and Stream Identifier per the protocol standard.

Precision time-stamping of the digitized elements is a key attribute of VITA 49.2. The Pentek IP automatically inserts timestamping information, per the VITA 49 standard, into the receiver stream data packets. The timestamp is applied at the A/D capture stage to generate the most accurate event capture time possible, regardless of data processing time. A variety of timestamping methods enable optimization for specific applications including GPS data overlay. For transmitted data packets with VITA 49 information, the output will have the header, stream ID, timestamp and trailer information removed, delivering only the payload signal data to the D/A converter for transmission.

“The VITA 49 standards fill a huge gap in protocol standards for data transport in RF applications,” stated Jerry Gipper, VITA executive director. “The standards are gaining acceptance in a rapidly growing number of applications and are being added to requirements in DoD platforms and test equipment.”

“The rapid acceptance of VITA 49.2 makes this an opportune time to add this IP to our Navigator development tools,” said Robert Sgandurra, director of Product Management. He added, “Our existing IP provided much of this functionality, but this is a more formalized method of providing the data per a widely implemented standard. Paul Mesibov, CTO and co-founder of Pentek, continues to be a key contributor to the development of the VITA Radio Transport series of standards and is also working with many of the other organizations to incorporate VITA 49.2 into their standards.”

Navigator Design Suite for Streamlined IP Development

Pentek’s Navigator™ Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator greatly speeds development tasks. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.

Pre-Configured SPARK System Ready for Immediate Use

SPARK^® development systems are ready for immediate operation with software and hardware installed. In many applications, the SPARK development system can become the final deployed application platform.

Form Factors, Pricing and Availability

The Models 71141 and 71851 are offered in commercial and rugged versions and are available in XMC, cPCI, VPX, AMC and PCIe form factors with a lead time of 8 to 12 weeks ARO. The VITA 49.2 IP is free with the Navigator Design Suite. The Navigator BSP is $2,500 USD and the Navigator FDK is $3,500 USD.