THERMAL DESIGN CONSIDERATIONS FOR WIDE BANDGAP TRANSISTORS
Abstract:
The peak junction temperature of a transistor is an important factor in determining its lifetime and output power degradation over time. Many design parameters determine the temperature rise in the semiconductor, including the transistor performance, semiconductor material and device dimensions. Thermal issues are of particular concern in wide bandgap transistors due to their intrinsic high power density. This article investigates the effect the number of gate fingers, gate geometry and epitaxial layer thickness has on the peak junction temperature of high power gallium nitride (GaN) and silicon carbide (SiC) transistors.1
Future radar and communications systems will require devices with significant improvement in output power over current technology. Wide bandgap semiconductors will be used in many of these applications. Small periphery, wide bandgap transistors have achieved an order of magnitude increase in power density over typical GaAs power transistors.2,3 The temperature of larger periphery devices can be significantly higher than small periphery devices due to thermal coupling between gate fingers. A thorough understanding of thermal modeling and associated device design issues is critical to achieving high power densities with large periphery devices.
The method of images is used in this article to calculate peak junction temperatures, and accounts for the temperature rise due to the power dissipated by a single gate as well as the contribution of heat from surrounding gate fingers.4 This contribution is significant for accurately modeling the peak junction temperature. The method of images provides the accuracy of finite element techniques with a comparatively significant reduction in the time required for problem definition and simulation.
The method of images used here predicts the temperature rise through one layer of material and not the overall peak junction temperature due to all of the layers in the thermal path. However, it permits accurate and efficient calculation of the peak junction temperature rise in the semiconductor substrate, which is typically the largest contributor to the overall temperature rise. Temperature rises in the other layers of the thermal stackup are created by differences in the packaging, not the semiconductor. Device power density, efficiency, thermal conductivity and dimensions, shown in Figure 1, are all that is required to determine the temperature rise.
Fig. 1 Transistor dimensions.
At 25°C, the thermal conductivity, K0, of GaN is 1.3 W/cm°C and the semi-insulating, SiC substrate is 3.3 W/cm°C. Thermal conductivity is temperature dependent and given by Kt(T) = K0 (300/T), where the device temperature, T, is in Kelvins.4,5 The temperature rise due to the temperature dependence of the thermal conductivity is given by T = T0 (eT/T0), where T0 is the baseplate temperature in Kelvins and T is the temperature rise in degrees Celsius.
THERMAL SENSITIVITY TO THE NUMBER OF GATE FINGERS
The temperature of a device is dependent on the number of gate fingers used in the transistor. When the gate pitch is sufficiently small and the substrate is thick enough to allow heat spreading, the heat sources will couple. Coupling will increase the temperature of a multiple-finger device compared to the temperature of a single-finger device. Thus, thermal coupling will degrade the power density as the number of gate fingers increases.
|
TABLE I | |
|
Gate Fingers |
Temperature (¡C) |
|
1 |
37 |
|
4 |
52 |
|
10 |
73 |
|
20 |
80 |
|
25 |
81 |
|
50 |
82 |
|
75 |
82 |
|
100 |
82 |
In this effort, the number of gate fingers was varied to assess their effect on peak junction temperature. The first example used a 100-mm-thick SiC substrate. The gate length was set to 0.35 mm with a gate width of 125 mm to represent dimensions typically used at X band. Each device had a pitch of 20 mm. Power density was set to 5.0 W/mm2 and transistor efficiency was assumed to be 50 percent.2 The X-band efficiency assumed is much higher than that achieved with SiC and will require future development. Table 1 lists the device peak junction temperature calculated using these parameters for 1, 4, 10, 20, 25, 50, 75 and 100 gate fingers. Table 2 lists a similar analysis performed with a 0.5 mm gate length and 400 mm gate width to represent devices at S band with all of the other parameters held constant. In this case, the SiC efficiency is similar to demonstrated levels.
|
TABLE II | |
|
Gate Fingers |
Temperature (¡C) |
|
1 |
37 |
|
4 |
59 |
|
10 |
89 |
|
20 |
104 |
|
25 |
106 |
|
50 |
108 |
|
75 |
108 |
|
100 |
108 |
The data show that there is a significant difference in peak junction temperature for as many as 20 gate fingers in X- and S-band devices. This result is important since large periphery devices are designed by scaling measured power densities in small periphery transistors. Measured power densities from 20-finger devices with the selected gate pitch could be used to estimate the output power performance of larger periphery devices.
THERMAL SENSITIVITY TO GATE PITCH
Thermal coupling between gate fingers is reduced as the gate pitch increases. The gate pitch plays an important role in determining the device's peak junction temperature. Gate pitch also determines the width of a high power device. Accordingly, the area of a high power transistor or MMIC is directly proportional to the gate pitch. A small gate pitch will reduce size and cost, but a minimum pitch must be maintained for thermal management.
The gate pitch was varied to assess its effect on high power density devices. The first gate pitch example uses devices with the same X-band gate dimensions used previously. In this case, both 100-mm-thick SiC and GaN substrates were analyzed. The number of gate fingers for each substrate was set to 100. The power density for both semiconductors was set to 5.0 W/mm2, and the transistor efficiency was assumed to be 50 percent.3 Table 3 shows the peak device junction temperature with the prior parameters for a 20, 30 and 40 mm pitch. The peak junction temperature of the X-band SiC transistor with a gate pitch of 20 mm is 81°C lower than the comparable GaN transistor with a pitch of 40 mm. SiC devices provide a significantly lower peak junction temperature at X band while requiring less than one-half the area of a device on a GaN substrate if equivalent efficiency can be achieved.
A similar analysis was performed with the prior S-band gate length and width. All of the other parameters used previously were maintained and the results are listed in Table 4. At S band, the GaN substrate requires at least twice the device area with a > 100°C temperature increase as compared to that on a SiC substrate. In this case, the excessive SiC temperature with a gate pitch of 20 mm would likely force a pitch greater than 30 mm.
While wide bandgap devices may operate reliably at temperatures higher than GaAs devices, the output power degrades with temperature. It is likely that a peak junction temperature similar to GaAs devices will be necessary to achieve the required performance. Excessive peak junction temperatures will preclude the use of GaN wafers for high power, high power density S- and X-band transistors with conventional die attachment techniques. SiC will require improvements in X-band efficiency for thermal management.
|
TABLE III | ||
|
Gate Pitch (mm) |
Temperature (¡C) | |
|
GaN |
20 |
213 |
|
30 |
156 | |
|
40 |
131 | |
|
SiC |
20 |
82 |
|
30 |
62 | |
|
40 |
53 | |
|
TABLE IV | ||
|
Gate Pitch (mm) |
Temperature (¡C) | |
|
GaN |
20 |
296 |
|
30 |
202 | |
|
40 |
163 | |
|
SiC |
20 |
108 |
|
30 |
78 | |
|
40 |
65 | |
|
TABLE V | ||
|
Epitaxial Thickness (mm) |
Temperature (¡C) | |
|
GaN |
1 |
34 |
|
2 |
43 | |
|
4 |
51 | |
|
SiC |
1 |
15 |
|
2 |
19 | |
|
4 |
22 | |
|
TABLE VI | ||
|
Epitaxial Thickness (mm) |
Temperature (¡C) | |
|
GaN |
1 |
32 |
|
2 |
40 | |
|
4 |
49 | |
|
SiC |
1 |
14 |
|
2 |
18 | |
|
4 |
21 | |
THERMAL SENSITIVITY TO SUBSTRATE THICKNESS
Growth of an epitaxial layer of GaN onto a SiC substrate is one technique to overcome the excessive thermal resistance of a GaN substrate. An analysis was performed with the same X- and S-band gate parameters with SiC and GaN epitaxial layer thicknesses set to 1, 2 and 4 mm. A gate pitch of 20 mm was used for all cases, and the results are listed in Tables 5 and 6. The thin layers analyzed do not permit thermal coupling at a typical gate pitch. Additional temperature rise in the semiconductor substrate beneath the epitaxial layer can be assumed constant for both cases if they are on SiC substrates.
This calculation shows that a significant temperature increase occurs in the first few microns of material and predicts that GaN will have a 30°C higher temperature rise than a SiC layer of similar thickness. This additional temperature rise does not prohibit the use of a GaN epitaxial layer on a SiC substrate, but demonstrates the performance advantage for SiC. The epitaxial layer thickness of the GaN is also a critical thermal design parameter.
FLIP-CHIP DIE ATTACHMENT
Flip-chip die attachment can eliminate the GaN wafer or sapphire substrate from the thermal path of a GaN epitaxial layer device. Heat generated in the flip-chip GaN epitaxial layer underneath the gate moves laterally to the source heat sink. This lateral movement restricts the spreading of heat within the epitaxial layer, as shown in Figure 2. The heat restriction increases the junction temperature rise experienced in the epitaxial layer when compared to a conventionally mounted device. A flip-chip is also mounted onto an electrical insulator to enable electrical contact to the gate and drain. The electrical insulators with the highest thermal conductivity are aluminum nitride (AlN) and beryllium oxide (BeO) at 1.7 and 2.15 W/cm°C, respectively. Both insulators have lower thermal conductivity than SiC. This temperature rise through the insulator can be much higher than through the SiC wafer for a conventional GaN device fabricated on a SiC wafer.
A finite element model of a flip-chip GaN device was used to evaluate flip-chip thermal issues. A 75-mm-thick GaN substrate was analyzed. The thickness of the semiconductor wafer has little or no effect on the flip-chip device's thermal resistance since the thermal spreading will not enter the substrate. The gate length was set to 0.35 mm with a gate width of 125 mm, again to represent dimensions typically used at X band. One hundred gate fingers were used with a gate pitch of 30 mm. Power density was set to 5.0 W/mm2, and transistor efficiency was assumed to be 50 percent. The source heat sink is 100 mm high, and the device was attached with a 5-mm-thick layer of Au/Sn (80/20) solder. The source heat sink has a thermal conductivity of 4 W/cm°C to represent a silver-based material, and the solder's thermal conductivity is 2.4 W/cm/°C. A 0.015"-thick AlN substrate was used as the insulator and mounted to a 0.040"-thick baseplate of copper molybdenum (20/80) with a thermal conductivity of 1.97 W/cm°C. The layers of AlN and CuMo must be extended beyond the layer of solder to allow the heat to spread, avoiding any additional temperature increase in the device. The resulting finite element plot is shown in Figure 3.
Fig. 2 Flip-chip cross section showing restricted heat flow from gate to source contacts.
Fig. 3 Finite element model of a flip-chip GaN device mounted on an AlN substrate and CuMo base plate showing heat flow.
The peak junction temperature of the flip-chip device is 274°C. A conventionally mounted device comprising GaN epitaxy on a SiC substrate does not have the restricted heat flow and insulating substrate limitations of flip-chip, and will likely become the preferred approach to realize high power density, high periphery GaN devices.
Flip-chip attachment poses many other significant issues related to thermal management. Silver-based source heat sinks are often proposed to lower the device's thermal resistance. This method introduces electromigration issues due to the high field strengths associated with GaN devices that can be addressed by using a gold heat sink, but results in a junction temperature rise of 313°C for the prior example's parameters.
The junction temperature can be made lower if a higher thermal conductivity baseplate is used. This material must be matched to the coefficient of thermal expansion (CTE) of the substrate to ensure a reliable solder contact. Similarly, the electrically insulating substrate also must have a CTE reasonably matched to the semiconductor to prevent solder or device mechanical damage due to thermal stress.7,8 The difficulty in addressing these issues increases with device area and will be particularly challenging for large-area power devices. Finally, stress induced in the epitaxial layer from the flip-chip attachment also can create undesired piezoelectric effects.9
CONCLUSION
The method of images has been used to show how the number of gate fingers in a device affects peak junction temperature. By varying the number and pitch of the fingers, temperature rise due to one gate and the contributions due to thermal spreading from other gates are calculated. The results of this finite element modeling also show the influence of other device features such as power density, efficiency, material thermal conductivity and dimensions upon device lifetime and performance degradation.
References
1. G.J. Sullivan et al., "High-power 10 GHz Operation of AlGaN HFETs on Insulating SiC," IEEE Electron Device Letters, June 1998, pp. 198–200.
2. S.T. Allen et al., "Recent Progress in SiC Microwave MESFETs," Proceedings of the Materials Research Society, Vol. 572, April 1999.
3. S.T. Sheppard et al., "High-power Microwave GaN/AlGaN HEMTs on Semi-insulating SiC Substrates," IEEE Electron Device Letters, April 1999, pp. 161–163.
4. D. Dawson, "Thermal Modeling, Measurements and Design Considerations of GaAs Microwave Devices," IEEE GaAs Symposium Proceedings, 1994, pp. 285–290.
5. Private conversation, Dr. Scott Allen, Cree Research Inc.
6. J.J. Xu et al., "1–8 GHz GaN-based Power Amplifier Using Flip-chip Bonding," IEEE Microwave and Guided Wave Letters, July 1999, pp. 277–279.
7. J. Bedinger, "Microwave Flip Chip and BGA Technology," IEEE MTT-S 2000.
8. Zhang et al., "RF and Mechanical Characterization of Flip-chip Interconnect," IEEE MTT, December 1998, p. 2269–2275.
9. E.T. Yu et al., "Measurement of Piezoelectrically Induced Charge in GaN/AlGaN Heterostructure Field-effect Transistors," Applied Physics Letters, November 1997, pp. 2794–2796.
