Modeling 3-Port Center-Tapped Spiral Inductors for K-Band VCO

Three-port center-tapped spiral inductors are designed to achieve high performance with symmetrically octagonal twin shapes for a K-Band voltage-controlled oscillator (VCO) in 0.13 µm SiGe BiCMOS technology. The modeling of on-chip inductors includes a 3D physical model for actual chip fabrication and a double π equivalent circuit model for precise parameter extraction. Simulation results for the physical and circuit models agree closely. The total inductance is 300 pH with a high Q of 18 at the desired operating frequency of 20 GHz. A 20 GHz VCO for K-Band applications using 0.13 µm SiGe BiCMOS technology with a chip area of 0.22 mm2 was built to verify the accuracy of the inductor modeling. The tuning range of the VCO was 2.21 GHz, from 19.9 to 22.11 GHz. At 20.89 GHz, the measured phase noise at 100 kHz and 1 MHz offset frequencies was ‐52.26 and ‐92.07 dBc/Hz, respectively. VCO power dissipation was 27 mW with a 1.5 V supply.

On-chip spiral inductors are needed to meet the increasing demand for wireless products with high performance, low-power, low-cost and high levels of integration. They are widely used in radio frequency integrated circuits (RFIC) to provide appropriate inductance values with high quality factors (Q) and high self-resonances.¹

Due to the lack of an accurate high frequency model for on-chip inductors in 0.13 µm SiGe BiCMOS technology, modeling of on-chip spiral inductors for the design of RFICs should be carefully considered.² A 3D physical model was accurately designed to be a compact octagon shape for ease of implementation, and an equivalent circuit model was established to be a double π schematic for precise parameter extraction and circuit optimization.^3,4

Three-port symmetric spiral inductors with center taps are often employed for differential RFICs such as VCOs, low-noise amplifiers (LNA) and mixers. The center tap is connected to the center node of a symmetric inductor. The symmetric inductor is constructed with underpasses independent of the number of turns, to minimize the chip area; however, the underpasses and inter-layer vias increase parasitic resistance and capacitance, which inevitably degrades inductor Q, especially for high frequency applications.⁵ Compared with a symmetric inductor, a single-ended inductor usually has only one underpass. Therefore, to improve Q by reducing the number of underpasses, two single-ended spiral inductors can be used to realize a symmetric structure. The penalty is increased chip area. In this work, a three-port symmetric inductor with center tap is accurately modeled with two single-ended spiral inductors for use in a 0.13 µm SiGe BiCMOS K-Band VCO.

PHYSICAL INDUCTOR MODEL

The process cross section for a 0.13 µm SiGe BiCMOS passive circuit is illustrated in Figure 1a. From bottom to top, the process includes one polymer layer, five thin metal layers (M1 through M5) and two thick metal layers (TM1 and TM2), with a top via between TM1 and TM2. For a Si substrate, the thickness, dielectric constant and resistivity are 754 µm, 11.9 and 50 Ω-cm, respectively. The dielectric constant of oxide is 4.1. The top metal layer (TM2) is 3 µm thick and 10.76 µm above the Si substrate.

The difficulty in physical modeling stems from the complexity of the high frequency phenomena, i.e., eddy currents in the interconnects and the substrate losses in the silicon. The key to accurate physical modeling is the ability to identify relevant parasitics and their effects.⁶ Generally, inductors must be high Q. Inductor Q is enhanced by reducing the transmission losses caused by parasitic series resistance, which is frequency dependent due to the skin effect, and the parasitic shunt capacitance to the substrate. Transmission loss becomes more serious at high frequencies.

To achieve high Q, the design addressed the following considerations (see Figure 1b): The inductor is in the shape of a spiral octagon with three ports. For differential RFICs, a symmetric structure is built with two single-ended inductors, L₁ and L₂, having the common port connected to the center tap (port 3). This two, single-ended symmetric structure is implemented mainly by the top metal layer (TM2), with only two underpasses realized by metal layer TM1 and inner-layer vias between TM1 and TM2. This minimizes parasitic resistance and capacitance, to decrease transmission loss and improve Q. Physical parameters (width, space, inner diameter and number of turns) are adjusted to optimize performance.

Another consideration for reducing transmission loss is to place a ground plane above the Si substrate to prevent currents from parasitically coupling into it. As the distance of the ground plane to the inductor decreases, however, its parasitic capacitance increases, causing the performance to degrade from self resonance. An approach to solve this is to utilize the bottom metal layer (M1) as the ground plane, which is far away from the inductor layers.

EQUIVALENT CIRCUIT MODEL

Equivalent circuit models of spiral inductors utilizing lumped RLC elements, together with other design components, can be used effectively to evaluate electrical performance. Compared with the physical model simulated by an electromagnetic field solver, a lumped equivalent circuit model significantly decreases simulation time, for more rapid optimization.

To illustrate the equivalent circuit model, a 3D view of the symmetric inductor is shown in Figure 2. L_s1, R_s1, C_s1 and L_s2, R_s2, C_s2 represent the inductances, resistances and line-to-line capacitances of the spiral wires of inductors L₁ and L₂, respectively.^4,5 L_s3 and R_s3 denote the inductance and resistance of the center tap line. C_ox1,2,3 represent oxide capacitances between the inductor line and the substrate. C_sub1,2,3 and R_sub1,2,3 depict the capacitances and resistances in the Si substrate. C_ox1,2,3, C_sub1,2,3 and R_sub1,2,3 form the RC network to model ohmic loss in the substrate. The total C_ox, C_sub and R_sub can be calculated as follows:

where l_wire is the total physical length of the symmetric inductor, t_sub and tox represent the thickness of the substrate and the height of the metal layer and w is the inductor width.

Double π equivalent circuit models of inductors are extensively used to achieve wideband modeling accuracy,⁷ which significantly ensures circuit stability beyond the operating frequency range of the RFIC. Additionally, double π equivalent circuit models are built by frequency-independent RLC elements to achieve geometric scalability.^3,4 The double π equivalent circuit model corresponding to the physical structure in Figure 2 is shown in Figure 3. L_b1, R_b1 and L_b2, R_b2 are added to model skin and proximity effects of the inductors at high frequency. In this case, the coupling coefficient k can be regarded as minimal, because the distance between L₁ and L₂ is relatively large.

Focusing on differential RFICs operating in K-Band, the physical and equivalent circuit models are optimized to verify uniformity through electromagnetic and circuit simulations, respectively. For the physical model, the width, space, inner diameter and turns of the inductor (see Figure 1) are optimized to be 7, 3, 50 and 1.5 µm, respectively. For the double π equivalent circuit model, a numerical approach is adopted to accurately calculate the lumped elements for the ladder circuit.² Using this approach, calculation complexity is dramatically reduced. Parameters used for calculation are extracted and shown in Table 1.

L and Q are calculated using Equations 6 and 7

where Z_DD is equal to (Z₁₁ + Z₁₂ + Z₂₁ +Z₂₂)*0.5

Results of both models are compared in Figure 4 and agree well. The simulated total inductance of L₁ and L₂ is approximately 300 pH (150 pH each) and the Q is approximately 18 at the operating frequency of 20 GHz.

K-BAND VCO DESIGN

To evaluate the performance of the symmetric inductor, a 20 GHz VCO was designed for K-Band applications. Figure 5 shows the schematic of the 20 GHz VCO core and buffers.⁸ The differential LC VCO core is constructed with cross-coupled nMOS transistors M₁ and M₂, which provide the negative conductance to compensate the loss of the LC tank. Transistor M₃ is used as the tail current source to set the current of the VCO. The LC tank is built using spiral inductors L₁ and L₂ together with MOS varactors C₁ and C₂. The MOS varactors are realized with a polysilicon-to-n-well structure, which has good linearity, high Q and a wide tuning ratio. The tuning ratio C_max/C_min is approximately 3 at 20 GHz, when the gate width, length and fingers of each varactor are selected to be 40 µm, 3 µm and 4, respectively. The output buffer of the VCO is a single-stage source follower amplifier, which has high input impedance to minimize loading of the VCO core and low output impedance to facilitate matching to a 50 Ω output.

The VCO design was fabricated on a 0.13 µm SiGe BiCMOS process having seven metal backends. The nMOS transistors used for low-power wireless applications achieve a cut-off frequency, f_T, around 100 GHz and a maximum oscillation frequency, f_MAX, around 130 GHz. The entire chip area, including testing pads, is 0.47 × 0.47 mm². One of differential outputs is terminated internally with an on-chip 50 Ω resistor, for measurement purposes.

On-wafer measurements were performed using a probe station with Cascade 100 µm G-S-G probes. Figure 6 shows the measured tuning characteristic of the VCO. The tuning range is 2.21 GHz, approximately 10.5 percent, from 19.9 to 22.11 GHz when V_ctrl changes from 0 to 1.5 V. The linear range is 0.96 GHz, from 20.56 to 21.52 GHz, when V_ctrl varies from 0.6 to 1 V. From this, the linear gain of the VCO is calculated to be 2.4 GHz/V.

The measured output spectrum over a 100 MHz span is shown in Figure 7. The output frequency was 20.89 GHz, with an output power of ‐21.9 dBm. Phase noise at 20.89 GHz is shown in Figure 8. At 100 kHz and 1 MHz offset frequencies from the carrier, the phase noise was ‐52.3 and ‐92.1 dBc/Hz, respectively. Using a 1.5 V supply voltage, the tail current of the VCO core was set at 4 mA, and the output buffers drew around 14 mA; hence, the total power dissipation of the VCO was 27 mW.

Table 2 compares the measured performance with simulation. The discrepancies between the simulated and measured results are attributed to losses from the probe, coaxial cable and SMA connector that reduce the output power and the parasitic effects of wire interconnects and signal pads that reduce the oscillating frequency, f₀, and tuning range and increase the phase noise. Hence, the interconnects for the VCO must be designed to be as short as possible, and the parasitic capacitance of the signal pads must be minimized.

CONCLUSION

Physical and circuit models were developed for a three-port symmetric spiral inductor with center tap. The performance of the two models agreed well and were designed and verified by fabricating a 20 GHz VCO, using a 0.13 µm SiGe BiCMOS process. The results show that the modeling approach described in this work provides a good estimate of L and Q for the highly integrated, differential RFIC designs.n

Acknowledgment

This work was supported by the Fundamental Research Funds for the Central Universities, Wuhan University (2042015kf0174 and 2042014kf0238); the Natural Science Foundation of Hubei Province, China (2014CFB694); the National Natural Science Fundamental of China (61204096 and 61404096); the China Postdoctoral Science Foundation (2012T50688) and the Science Fundamental of Jiangsu Province, China (BK20141218).

References

1. H. H. Chen, H. W. Zhan, S. J. Chung, J. T. Kuo and T. C. Wu, “Accurate Systematic Model-Parameter Extraction for On-Chip Spiral Inductors,” IEEE Transactions on Electron Devices, Vol. 55, No. 11, November 2008, pp. 3267–3273.
2. Y. G. Ahn, S. K. Kim, J. H. Chun and B. S. Kim, “Efficient Scalable Modeling of Double-π Equivalent Circuit for On-Chip Spiral Inductors,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 10, October 2009, pp. 2289–2300.
3. Y. Cao, R. A. Groves, X. Huang, N. D. Zamdmer, J. O. Plouchart, R. A. Wachnik, T. J. King and C. Hu, “Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral Inductors,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, March 2003, pp. 419–426.
4. W. Y. Lim, M. A. Arasu and M. K. Raja, “Modeling of Two Port Center-Tapped to Ground and Three Port Scalable Symmetrical Inductor,” 14th International Symposium on Integrated Circuits, December 2014, pp. 540–543.
5. J. Chen and J. J. Liou, “Improved and Physics-Based Model for Symmetrical Spiral Inductors,” IEEE Transactions on Electron Devices, Vol. 53, No. 6, June 2006, pp. 1300–1309.
6. C. P. Yue and S. S. Wong, “Physical Modeling of Spiral Inductors on Silicon,” IEEE Transactions on Electron Devices, Vol. 47, No. 3, March 2000, pp. 560–568.
7. W. Gao and Z. Yu, “Scalable Compact Circuit Model and Synthesis for RF CMOS Spiral Inductors,” IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 3, March 2006, pp. 1055–1064.
8. J. He, J. Li, D. Hou, Y. Z. Xiong, D. L. Yan, M. A. Arasu and M. Je, “A 20 GHz VCO for PLL synthesizer in 0.13-μm BiCMOS,” IEEE International Symposium on Radio-Frequency Integration Technology, November 2012, pp. 231–233.