One of the challenges of emerging technologies—5G and IoT are good examples—is the need for increased integration and functionality to meet the performance and cost requirements of these applications. This increased integration raises a new problem for RF and microwave designers: how to verify the integration. Fortunately, verification of complex designs is a problem that analog and mixed-signal designers have struggled with for years, and the best design practices have been automated in the Cadence® Virtuoso® Analog Design Environment (ADE).
The Virtuoso platform celebrated its 25th anniversary in 2016. Over that time, Virtuoso ADE became the standard design environment for custom IC design by automating the methodology for front-to-back custom IC block realization, including parasitic closure. In the latest refresh (IC6.1.7), ADE has been enhanced to focus on optimized solutions for each design phase.
The Virtuoso ADE Product Suite has been organized into three tiers: Virtuoso ADE Explorer, Virtuoso ADE Assembler and Virtuoso ADE Verifier.
- ADE Explorer is an interactive design environment that includes basic variation analysis and new tools for debugging and design tuning
- ADE Assembler is also an interactive environment used for design validation under a multitude of different conditions, and
- ADE Verifier maps design requirements from customers to the tests being performed in the regression suite to verify that the requirements are satisfied.
Figure 1 Real-time tuning in ADE Explorer.
For analog and mixed-signal designers, Spectre® APS is the simulator of choice for design and verification. The Spectre RF option makes the Spectre APS technology accessible to RF and microwave designers by providing designers fast and high capacity harmonic balance analysis. This integration of RF analyses with advanced analog and mixed-signal design tools supports the needs of RF designers who are challenged with high frequency designs using planar CMOS processes.
Figure 2 Interactive debugging in ADE Explorer.
Figure 3 Monte Carlo analysis example.
NEW EXPLORER TOOLS
Looking at some of the new features of Virtuoso ADE in IC6.1.7, in the first example, ADE Explorer is used to design a low noise amplifier (LNA). ADE Explorer has been developed based on extensive interactions with designers to optimize their use model for interactive design. Overlaid on top of this environment are tools for RF designers such as real-time tuning and specialized measurements. Consider the problem of tuning an input matching network to optimize S11 (see Figure 1). Designers can use slider bars to interactively explore the design space and compare the current results with the previous results. In addition to real-time tuning, designers also have access to Explorer’s new interactive debugging capabilities. Suppose that the LNA stops working. A designer can add waveform bubbles to the schematic to monitor key nodes in the circuit, identifying at which node the design “stops wiggling.” Once the designer identifies where the issue is, the operating point information can be displayed in a table by simply hovering over the devices (see Figure 2).
Figure 4 Contribution analysis example.
Another significant new feature in Virtuoso ADE Explorer is support for process corners and statistical variation simulation. Two options are provided for Monte Carlo analysis: choosing the number of iterations or using Monte Carlo analysis with auto-stop (see Figure 3). Virtuoso ADE also provides advanced tools to analyze the relationship between statistical variation and circuit performance. The Virtuoso Variation option provides contribution analysis. Contribution analysis replaces sensitivity analysis and maps the linear and nonlinear input variations to the output variations (see Figure 4). For example, from the Monte Carlo results, the power supply current (Idd) has a second-order dependency on variation, and the dominate source of variation in the power supply current is rshhip, the sheet resistivity of the high resistance polysilicon. Other views of the data can show other dependencies, for example, which blocks are the source of variation. As designs become more complex, the relationship between cause and effect becomes more difficult for designers to readily identify, and contribution analysis provides a useful tool to identify the core trouble area faster. Back to real-time tuning, contribution analysis can be used to define the parameters to be tuned. The final block-level verification can be run and specification compliance verified (see Figure 5).
Figure 5 Corner analysis example.
ADE ASSEMBLER AND VERIFIER
Virtuoso ADE Assembler provides significant new functionality for design validation, particularly the ability of run plans to run multiple variants of a test bench. For example, to characterize the signal-to-noise + distortion ratio (SINAD) of an analog-to-digital converter (ADC) may require measuring distortion across process, voltage and temperature (PVT) corners and the effect of capacitor mismatch using Monte Carlo analysis. Another common application of Virtuoso ADE Assembler is to validate digitally assisted designs. For example, suppose the designer is using an integrated channel filter for a receiver. The bandpass filter is implemented with five bi-quad sections. The channel filter needs to be controlled to ±1 percent, but the process variation of the on-chip R and C components is 30 percent. The solution is to tune the R and C values in the design to compensate for process variation. Using calibration, we get all the advantages of an off-chip filter with an integrated component. Regular calibration means that the effects of phenomena such as temperature drift are eliminated. In the example shown in Figure 6, the last resonator in a bandpass filter is turned into an oscillator, and the frequency of the oscillator is tuned (see Figure 6c). Tuning is achieved by replacing the capacitor in the filter with capacitor digital-to-analog converters (DAC). Digital control is used to tune the CAPDAC value to the target frequency and then code all the bi-quad sections to be set to the tuned value. An example of tuning the filter is shown in Figure 6d. The filter frequency and filter bandwidth meet the specification after tuning.
Figure 6 Channel filter with calibration (a) and bi-quad section with calibration (b). Tuning the oscillator frequency (c), tuning the frequency filter response (d).
Virtuoso ADE Verifier addresses long-standing gaps in the existing design methodologies. ADE Verifier provides requirements management, allowing project managers to visualize the completeness of product validation (see Figure 7). Automotive standards such as ISO26262 and equivalent standards for medical and military/aerospace applications require mapping the system-level requirements to product-level requirements, then showing how the requirements will be tested and compliance validated. Going back to the ADC example discussed earlier, the system-level requirement may be to achieve a SINAD of 60 dB or better at the Nyquist frequency. To calculate the SINAD, several simulations may be required: distortion across PVT corners, comparator noise across process variation, capacitor mismatch across mismatch and others. Virtuoso ADE Assembler provides the first solution for automating the tracking of requirements and the status of a project.
Figure 7 Virtuoso ADE Verifier.
Release IC6.1.7 of Virtuoso ADE brings new technologies that RF and microwave engineers can use to address the challenge of designing and validating 5G and IoT designs. The three new tools—ADE Explorer for design, ADE Assembler for validation and ADE Verifier for oversight—enable product development to be better managed and accelerated.
Cadence Design Systems Inc.
San Jose, Calif.
www.cadence.com