5 W, Ku-Band GaAs T/R MMIC with Switch Topology

A power amplifier (PA), low noise amplifier (LNA) and two switches are integrated in a single GaAs PHEMT Ku-Band transceiver (T/R) MMIC, which can be used for phased array systems. A novel topology increases the power handling capability of the switch without increasing insertion loss. High saturated power (greater than 5 W) and very low noise figure (less than 3.3 dB) are achieved in the frequency range of 14.5 to 17 GHz. The size of the MMIC is 3 mm × 4 mm.

Market growth in active phased array (AESA) radar has created a large need for multi-function T/R chips.^1-4 T/R chips based on the Si CMOS process currently enable higher integration levels than counterparts based on the GaAs PHEMT process. However, RF performance of Si-based chips, such as output power, power-added efficiency (PAE) and noise figure, is poorer than that of GaAs-based chips. Van Vliet and De Boer³ developed a GaAs T/R chip containing a driver amplifier, LNA, phase shifter and attenuator; however, its power and noise figure are not given. A T/R chip with wide bandwidth was presented by Bettidi et al.,⁴ but its output power was only 20 dBm. The limited output power was due mainly to low P1dB performance of the traditional GaAs FET switch.^5-8

To address these problems, a T/R chip with high output power and low noise figure is presented here. The switch is based on a novel topology, which increases its power handling capability without increasing insertion loss. Measurement results show that saturated power (Psat) and gain of the transmitting branch of the T/R chip are more than 5 W and 15 dB, respectively, while noise figure and gain of the receiving branch are better than 3.3 dB and 18 dB, respectively, in the frequency range from 14.5 to 17 GHz.

CIRCUIT CONFIGURATION AND DESIGN

The T/R chip architecture contains a PA, LNA and two T/R switches (see Figure 1). The PA has two amplifier stages: 16 transistors with 8 × 125 μm gate width and eight transistors with 6 × 125 μm gate width at the output and input stages, respectively. Good input return loss is obtained by tuning the input matching network. Sufficient output power to drive the output stage is realized by proper design of the interstage matching network. Maximum output power is achieved through matching circuit design based on load-pull simulation using the nonlinear model of the active device. Figure 2 shows the optimum load impedance of the output stage transistor corresponding to maximum saturated power in the range from 15 to 17 GHz, along with the output matching network frequency response; their close correspondance implies that a wide power matching bandwidth can be achieved.

The LNA contains three stages; the gate width of the transistor in each stage is 2 × 25 μm. Bias voltages are selected with the aid of Agilent ADS software to ensure that the active devices operate in their low noise regions; the gate-source voltages (V_gs) and drain-sources voltages (V_ds) are set at -1 V and +3 V, respectively. The input matching network is designed to achieve a low noise figure, while interstage and output matching networks are designed for high gain.

At the antenna side of the circuit, a novel topology single pole double throw switch (SPDT2 in Figure 1) selects the transmit or receive branch. At the input, an off-chip SPDT switch (SPDT1) with traditional parallel topology selects transmit or receive. SPDT2 is the key device, consisting of a λ/4 transmission line and FET with a gate width of 4 × 100 μm (see Figure 3). When transmitting, the FET is turned on and is equivalent to a small shunt resistor (R_on), as shown in Figure 3a. RF power leaks to the FET through the λ/4 transmission line. If the voltage magnitude of the leaked RF signal is greater than the knee voltage of the FET, the switch is compressed. In this design, the leaked RF power at the FET can be decreased by tuning the characteristic impedance (Z_r) of the λ/4 transmission line to increase the power handling capability of SPDT2, enabling increased output power from the T/R MMIC. An optimized Z_r of 112 Ω is chosen. The shunt capacitor (C₁) is also designed to tune the impedance at point B. When receiving, the FET is turned off and is equivalent to a shunt capacitance (C_off), as shown in Figure 3b. The active devices in the last stage of the PA are equivalent to a parallel resistor and capacitor (R_ds and C_ds). All of these components are used as part of the input matching circuit of the LNA. A low LNA noise figure is obtained by tuning transmission lines TL₁ and TL₂.

This design decreases the insertion loss of the output matching network due to the shorter transmission line. By optimizing the impedance at point B, the power handling capability of the switch can be improved without widening the gate width of the FET. This is explained as follows: Assume that the characteristic impedances of stubs L₁ and L₂ are both Z_t. The characteristic impedance of the λ/4 transmission line (L₃) at the receiving branch is Z_r, and the on resistance of the switching FET is R_on. In the transmitting branch, the impedance Z₁ at point B is given by:

In the receiving branch, the impedance Z₃ is given by:

Because R_on is very small, Z₃ is a very high impedance compared to Z₁. In the design, therefore, it is just necessary to ensure that impedances Z₁ and Z₂ are conjugately matched:

The voltage magnitude at point D of the RF signal in the transmitting branch is given by Equation 4:

where P_A is the output power at point A. The voltage magnitude of the leaked RF signal at the switching FET in the receiving branch is given by Equation 5.

To keep the switch operating in the linear region, V_C ≤ V_knee, where V_knee is the knee voltage of the switching FET. Equation 5 shows that for a given P_A, V_C is affected mainly by three parameters (R_on, Z₁ and Z_r). R_on is determined by the gate width of the switching FET, Z₁ is determined by the output matching network design and Z_r is determined by the width of transmission line L₃ in the receiving branch.

Equation 5 also shows that V_C is proportional to P_A, R_on and Z₁ and is inversely proportional to Z_r. For a given P_A, the switch can be operated without being compressed by carefully choosing Z₁ and Z_r. The shunt capacitor C₁ is optimized to decrease the modulus of Z₁. The gate width of the FET is chosen to be 2 × 100 μm. The knee voltage of the 0.15 μm PHEMT process is about 0.9 V, which means that if the RF leakage voltage at the drain port of the FET is less than 0.9 V, the switch will exhibit good linearity.

To test the validity of this method, the power handling capability of this switch design is simulated in Keysight ADS and compared to a typical SPDT switch. In this topology, the switch and output matching network of the PA are designed together. Unlike a typical design (see Figure 4a), there is no λ/4 transmission line and shunt FET placed at the output of the transmitting branch (see Figure 4b). Figure 4c shows that the 1 dB compression point of the new switch is 39 dBm compared to 25.5 dBm for the typical parallel configuration, demonstrating a significant improvement. The gate widths of the FETs in the two designs are the same.

MEASURED RESULTS

The Ku-Band GaAs T/R MMIC is fabricated using a 0.25 μm GaAs PHEMT process and measures 3 mm × 4 mm (see Figure 5). The performance of the design is measured on wafer with a Cascade M150 probe station and a Cascade ACP40-A Ku-Band GSG probe under pulsed conditions, with 0.2 ms pulse width and 10 percent duty cycle (see Figure 6). A vector network analyzer is used to measure the small-signal response and a signal generator and microwave power meter are used for the large-signal measurements. Figure 7 shows the simulated and measured small-signal and large-signal responses of the transmit path. Measured small-signal gain, large-signal gain, Psat and PAE are better than 15 dB, 10 dB, 37 dBm and 17 percent, respectively. The measured small-signal gain and noise figure of the receiving branch are greater than 18 dB and less than 3.3 dB, respectively (see Figure 8). Figure 9 confirms that the T/R MMIC does not saturate below 5 W.

CONCLUSION

A Ku-Band T/R MMIC, proposed for use in AESA systems, employs a novel SPDT switch with improved power handling and low insertion loss to realize higher transmitter power and lower receiver noise figure.

ACKNOWLEDGMENT

T/R chip measurement was supported by RML Technology Company Ltd.

References

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