SiGe Transistor Technology for RF Applications

SiGe Transistor Technology for RF Applications

Dilek Barlas, Gregory Henderson and Xiandong Zhang
M/A-COM
Lowell, MA

Matthias Bopp and Andreas Schüppen
Temic Semiconductors, an Atmel company
Heilbronn, Germany

Demand for mobile communications during the last decade has been driving the explosive interest for radio frequency integrated circuits (RFIC). The consumer nature of the market demands the implementation of RF functions in a small size with user-friendly features at low cost, low power and high volume.

Although focused research is being conducted in zero-IF radios, the majority of second- and third-generation radios are likely to utilize traditional architectures by leveraging ongoing performance, integration and manufacturing cost improvements. For the designers of these systems, there are various technology choices to leverage performance vs. cost, as shown in Figure 1 .

Today's digital communication systems with high data rates and large bandwidth requirements demand receiver designs with increasing dynamic range and transmitters with efficient linear power amplifiers. The challenge to the RFIC designer and semiconductor device technologist is that these conditions must be met with constantly decreasing operating power levels and manufacturing cost. For example, if the noise figure of the mixer in the receiver is lowered while keeping the large-signal capability high, then the gain of the preamplifier can be reduced without sacrificing system sensitivity.

Under these conditions, the designer can also lower the input third-order intercept point (IIP3) of the mixer without compromising the overall large-signal capability. Consequently, power consumption of the receiver can be reduced or some trade-off between power consumption and cost can be achieved by relaxing the requirements on the filter performance. If the power consumption is sufficiently low, costly passive filters can be further eliminated by employing image-reject mixers in the system design. In short, a device technology with high performance and low power consumption is the key to meeting this challenge.

Performance improvements in silicon ICs have been largely achieved via reductions in geometry and the corresponding low energy implantation processes. In SiGe technology, incorporation of germanium into the base region of the transistor opens up new avenues to the device designer to improve frequency response, gain and linearity without the standard constraints of an implanted process. A key figure of merit of a transistor is fT. Today's silicon technology routinely yields an fT > 30 GHz. However, this improvement comes at the expense of increased base resistance and reduced Early voltage (linearity), both of which are detrimental to RF performance. This article discusses how SiGe can help alleviate some of these constraints.

SiGe technology has been evolving over the last decade and a half, driven primarily by the works of B. Meyerson and his colleagues at IBM.¹ During the last few years, many lively debates about the pros and cons of the technology have taken place.² In addition, Daimler Benz and Temic Semiconductors have developed a proprietary process targeting wireless applications rather than pure digital performance. As is typical for new technology, the rate of product introduction has been slower than promised, although this rate has started to change significantly during the last six months. More companies are relying on SiGe now that its performance and manufacturability are proven. One of the reasons for this quick ramp up is the rather straightforward conversion of bipolar RF circuits designed in pure silicon bipolar technology into SiGe technology. As a result, many designers are benefiting from their existing experience in contrast to designing new circuits in CMOS. Time to market will be the benefit for the system designers.

The aim of this article is to examine SiGe and its relationship to standard bipolar and CMOS technologies. The major advantage of and opportunity for SiGe are that it can be easily integrated into standard bipolar and bipolar-CMOS processes with minimal cost impact. This ability allows the device and circuit designer to improve both the CMOS and heterojunction bipolar devices with respect to power, noise and speed. It is these possibilities that make the technology attractive to wireless markets.

In the following sections, the transistor, process and circuit design trade-offs for SiGe will be examined. First, the basic advantages of SiGe (both true heterojunction bipolar transistors (HBT) and graded-base devices) over conventional bipolar devices will be reviewed. Then, the more subtle design trade-offs will be investigated, followed by performance examples of both low voltage devices for RFICs and PAs and high voltage devices for wireless base station applications.

Advantages of SiGe-HBTs over BJTs

The performance advantages of SiGe over pure silicon for RFIC applications are mainly the extremely high cutoff frequencies with reported fT = 130 GHz³ and fmax = 160 GHz characteristics⁴ and current-mode logic gate delay down to 7.7 ps.⁵ Furthermore, improved power-added efficiency (PAE) at low DC voltages makes SiGe HBTs a good choice for power amplifier applications. The economic advantage of SiGe HBTs over III-V HBTs is that a standard Si production line and most of the standard bipolar process modules can be used for device fabrication. This capability allows low cost production in existing silicon fabs with high yield and good proven reliability.

SiGe bipolar junction transistors (BJT) are, in principle, bipolar transistors; the only difference is the presence of germanium in the base region, which reduces the band gap of the SiGe material. Two types of SiGe BJTs have been demonstrated: a graded-base BJT (pioneered by IBM1) and a true box-profile HBT (pioneered by Daimler2). Conceptual doping profiles for these two processes are shown in Figure 2 . In both processes, the addition of Ge in the base allows for a reduced base transit time for a given base sheet resistance, thus providing a device with simultaneously high fT and fmax, as shown in Figure 3 . The higher base doping concentration provides advantages in both a higher Early voltage (due to less modulation of the space region into the neutral base) and a low noise figure (due to the low Rb and high b), which translate into performance advantages for RF applications.

Process Technology

The technology, performance and application of two SiGe processes will be reviewed. The first example is a low voltage IC process (true HBT) in production at Temic Semiconductors, which includes npn HBTs with and without a selectively implanted collector (SIC) on the same wafer.^6,7 The second example is a high voltage discrete BJT process (graded-base BJT), which is in development at M/A-COM for high voltage (Vc = 10 to 30 V) RF power applications.

The SiGe1 IC Process

The SiGe1 IC process was developed for RFICs with Vc = 1.5 to 5 V application voltages. A schematic drawing of the process is shown in Figure 4 for a SiGe1 HBT with BVECO = 6 V (fT/fmax = 30/50 GHz), 3 V (fT/fmax = 50/50 GHz). The process' main technological advantage is the differential growth of the SiGe layer after a standard recessed local-oxidation-of-silicon process. The SiGe-poly is used for the base contact and for two of the three resistor types. The emitter has an inside and outside spacer and an additional amorphous Si layer, which is used to form the emitter and collector contacts. In addition, spiral inductors, nitride capacitors, three types of poly resistors, a lateral pnp transistor, RF- and DC-electrostatic discharge protection, and varactor diodes are incorporated in the present technology. The highly boron-doped SiGe base (4 ¥ 1019 cm-3), which is grown by a single wafer chemical vapor deposition machine, provides an extremely low base sheet resistance of 1.5 kW/sq. Hence, it is possible to use wide emitter stripes (up to 2 mm) for power HBTs.

The SiGe1 technology is comparable in terms of number of masks and process costs to a standard double-poly Si BJT process. Therefore, this technology provides an ideal platform for large-scale integration RFICs. The process has been fully qualified based on device lifetime and packaged circuit lifetimes.

The High Voltage SiGe BJT Process

Traditionally, SiGe has been perceived as an inherently low voltage technology since the process was developed for RFIC and digital applications. However, SiGe BJTs can obtain the same breakdown voltages as Si BJTs (Vcbo > 80 V and Vceo > 26 V) for RF applications. In addition, performance improvements from SiGe in linearity, efficiency and gain for high voltage wireless power applications have been demonstrated.

For Si power transistor applications such as base stations, the typical bipolar process, as shown in Figure 5 , starts with a heavily doped n+ substrate (collector contact), proceeds with n- collector epitaxy (collector) and concludes with a junction-isolated, traditional implanted base and emitter process. The doping and thickness of the collector (along with the radius of the junction isolation) control the breakdown voltage of the device. A SiGe power process has been developed that replaces the base implant step with SiGe epitaxy growth and uses a polysilicon emitter. Aside from these minor changes, the process is essentially the same as an implanted bipolar process. A 15 V SiGe power process has been demonstrated using this process flow with Vcbo > 50 V (55 V, typ) and Vceo > 15 V (18 V, typ).

RF Performance Results

Low Voltage SiGe1-to-DC and Small-signal Performance

The performance details of the SiGe1 low voltage process are listed in Table 1 . The SiGe HBTs reveal transit frequencies fT of 30 GHz with a collector-to-emitter breakdown voltage of BVCEO = 6 V and 50 GHz, respectively, with BVCEO = 3 V. The maximum fT and fmax values were achieved at current densities of 0.3 mA/mm2 and 0.65 mA/mm2 for the non-SIC and the SIC devices, respectively, as shown in Figure 6 . The SiGe1 process has demonstrated minimum noise figures of 0.8 dB and associated gain of 17 dB at 2 GHz, as shown in Figure 7 . One important advantage of SiGe-HBTs is that the matching impedance for the minimum noise figure is close to 50 W, making it easy to realize a low noise amplifier (LNA).

Table I Key SiGe RFIC Performance Parameters
	non-SIC	SIC
npn Transistor
Transit frequency fT (GHz)	30	50
Maximum frequency of oscillation fmax (GHz)	50	50
Current gain hFE	180	180
Early Voltage VA (V)	50	50
Collector-emitter breakdown voltage BVCE0 (V)	6	3
Collector-base breakdown voltage BVCB0 (V)	15	12
Noise figure at 2 GHz fmin (dB)	1	1
pnp Transistor
Collector-emitter breakdown voltage BVCE0 (V)	7
Current gain hFE	7
Typical collector current ICP (micro-A)	40
Passive Devices
High Ohmic poly resistor (poly1) RH (ohm/sq)	400
Medium Ohmic poly resistor (poly2) RM (ohm/sq)	110
Low Ohmic poly resistor (poly1 - TiSi2 ) RL (ohm/sq)	4.5
Precision MIM capacitor cSPEC (fF/micro-m2 )	1.1
Spiral inductor Q at 2 GHz (4 nH)	7
ESD zener diode, zener voltage VZ (V) zener diode, parasitic capacitance (pF)	6.2 5.5
RF-ESD diode, parasitic capacitance (pF)	0.3

Low Voltage SiGe1 Power Performance

The low voltage SiGe1 process has been characterized for power amplifier (PA) applications through on-wafer and packaged measurements. The device used for on-wafer RF power characterization is a 20-finger (3 ¥ 30 mm) common-emitter power cell of which the fT and fmax are 15 and 20 GHz, respectively. The reference planes of the load-pull system were calibrated to the device base/collector launch pads to measure the actual input and output impedances of the device. Table 2 lists the power and efficiency characteristics of this device with a 3 V collector bias under CW excitation at 900 MHz and 1.88 GHz, respectively. (The device loads were tuned for optimum PAE performance.) The devices achieved good efficiency of 72 percent at 900 MHz and 64 percent at 1.88 GHz at power levels of 0.25 to 0.35 W, indicating the suitability of the process to handset PAs.

Table II On-Wafer Test Results
Frequency (MHz)	900	1880
PAE(%)	72	64
Output power (mW)	350	250
Power gain (dB)	15.0	12.5

Multicell devices were housed in a ceramic package to allow for characterization at higher power levels. As shown in Figure 8 , the packaged device had internal input matching to increase the input impedance. Distributed prematching circuits were formed on Duroid low loss substrates to bring the input and output impedance level close to 50 W. The reference planes of the power test were calibrated to the fixture input/output connectors (outside the Duroid).         

Figure 9 shows a four-cell SiGe HBT's power performance as a function of input power at 900 MHz and 1.96 GHz under class B bias conditions. (Note that the power measurements include the package and fixtures loss.) Clearly, this 3 V fixtured device has demonstrated 66 percent PAE with 1.1 W output at 900 MHz, and 61 percent PAE with 800 mW output at 1.96 GHz.

High Voltage SiGe BJTs

The high voltage SiGe BJT process has been used to develop 15 V discrete power devices. The process has an fT = 8 GHz, Gmax (2 GHz) = 22 GHz, Vcbo = 55 V and Vceo = 18 V. The unit cell die in the process has an output power Po ~ 12 to 13 W, depending on the tuning. The power devices have been characterized using a ceramic package with input internal matching and external matching networks on a soft-board fixture to match to 50 W. Figure 10 shows an assembled two-die (~ 24 W) power device. At 1.96 GHz with 15 V/class B bias conditions, a single die achieves 53 percent PAE with P1dB at 12 W and 10 dB power gain. As shown in Figure 11 , the two-die device achieves 24 W Po, 9.7 dB gain and 49 percent PAE.

As described previously, SiGe provides an advantage to obtain high fT and fmax simultaneously, which improves the gain and efficiency over conventional Si BJTs. In addition, as SiGe has a more heavily doped base defined by epitaxy, the Early voltage for a SiGe device is significantly higher than for a power Si BJT, as shown in Figure 12 . These factors combine to provide better linearity for a SiGe BJT compared to a Si BJT.  

Figure 13 shows a power sweep under IS-95 CDMA modulation for the 15 V SiGe power BJT and a commercially available 30 W Si BJT. Both devices were tuned for maximum adjacent-channel power rejection (ACPR) ~ 11 dB back from P1dB, where the ACPR is defined as the power measured at 1.96 GHz in a 30 kHz bandwidth minus the power measured at 1.96 GHz ± 885 kHz in a 30 kHz bandwidth. The SiGe device has ~ 1 dB better gain and ~ 3 to 5 dB better linearity with roughly comparable efficiency.

In order to support device development (particularly for high power applications), extensive effort has been put into large-signal modeling. A modified Gummel-Poon model has been developed to simulate the nonlinear power characteristics of both low voltage and high voltage SiGe power devices. The model (conceptually shown in Figure 14 ) includes breakdown effects (which can significantly limit the available load conditions for the device under high power operation), fT reduction and maximum current limitation that come from the Kirk effect, and bond-wire and package parasitics (which play a  significant role in the high power device performance due to the low impedance involved (~ 0.1 to 0.5 W)).3 The model can accurately predict the power performance for both 15 V devices and 3 V power devices, as shown in Figure 15 .

IC Circuit Applications

As shown previously, SiGe HBTs are a suitable technology for the design of high performance analog ICs for RF systems from 1 to 10 GHz. The performance data shown in the previous sections indicate that SiGe can provide good performance at a reasonable cost for circuits such as LNAs, PAs, mixers, VCOs and phase-locked loops. High speed analog-to-digital and digital-to-analog converters also can be implemented in SiGe. In addition to offering increased performance, SiGe allows  fully integrated complementary circuitry such as biasing blocks and logic circuits to be added without significant cost penalties. This feature is the key to any cost-effective system solution.

LNAs

Using the SiGe1 process, LNAs have been designed from 1.9 to 10 GHz. Table 3 lists the IIP3 and P1dB performance; Figure 16 shows the measured 50 W noise figure for three LNAs designed for 1.9, 5.8 and 10 GHz operation. The gain of all three LNAs is greater than 10 dB with the 10 GHz LNA producing a gain of > 10 dB over a 3 GHz bandwidth.

 

Table III LNA Performance
Frequency (GHz)	1.9	5.7	10.0
Voltage (V)	4.5	4.5	3.6
Current (mA)	6.0	7.4	12.0
IIP3 (dBm)	-2.7	-13.0	-6.8
P1dB (dBm)	-11.0	-7.5	-9.0

PAs

In addition to LNAs, the SiGe1 process has been used to develop a three-stage fully integrated GSM PA including input matching, interstage matching, and biasing and power control circuitry. Only the output matching of the final stage is implemented on the PCB. The PA was designed to obtain > 40 dB of gain and a peak PAE of 50 percent, and maintain > 40 percent PAE over 6 dB of dynamic range in power control and a PAE of 50 percent for supply voltages from 2.4 to 5 V.            

Figure 17 shows the PA's performance data. The control range of the PA is approximately 40 dB. The control voltage is also used to shut down the PA and results in a standby current of below 1 mA while the PA remains connected to the supply rail, thus eliminating the high side switch that reduces the net PAE in FET-based PA solutions. This feature is especially important for low voltage operation where the complete integrated PA can achieve 50 percent PAE at supply voltages as low as 2.4 V.

General Packet Radio Service (GPRS), the next-generation GSM, will require multislot capability in both the transmit and receive modes. The degradation of the output power (in a 5 to 95 percent pulse window) was measured in both single- and multislot operation at Vc = 3.5, Pout = 34.4 dBm and Pin = 10 dBm. Due to the thermal design and good conductivity of silicon, the degradation under these pulsed conditions was minimal for single-, double- and triple-slot applications with a single-slot (12.5 percent duty cycle) power degradation of 0.04 dB, a double-slot (25 percent duty cycle) degradation of 0.07 dB and a triple-slot (37.5 percent duty cycle) degradation of 0.09 dB. Because of this good thermal performance, the SiGe GSM PA lends itself to flip-chip packaging, which improves the performance of the PA in terms of gain, PAE and output power due to reduced electrical parasitics. A first-generation flip-chip PAE, shown in Figure 18 , has demonstrated a PAE of 53 percent at peak power.

Transceivers

The SiGe1 process has been used to develop a highly integrated Digital Enhanced Cordless Telecommunications (DECT) front end, which is in production as part of a DECT chipset,⁸ as shown in Figure 19 . The front end includes an LNA in the receive path, a PA for the transmit path and a driver for an external PIN diode switch. The chip, shown in Figure 20 , provides a simple system solution operating from 2.7 to 5 V without negative supply voltage or external power management such as a high side switch.

In the transmit mode, the 0 dBm input signal is amplified to 26.5 dBm by the PA. The PA achieves a small-signal gain of 33 dB, maximum PAE of 41 percent and saturated output power of 26.5 dBm at a supply voltage of 3 V. The packaged chip (PSSOP16 package with a heat slug) can be operated in multislot mode (and even CW mode) due to the high thermal conductivity of silicon. Thus, this device is especially well suited for wireless local loop base stations or multimedia and data applications with highly asymmetrical up- and down-link requirements. The front-end chip exceeded the DECT system requirements and improved the receiver's overall sensitivity by 10 dB.

In receive mode, the signal is amplified by the LNA with a gain of 19 dB and a noise figure of 1.7 dB with minimal off-chip matching. Figure 21 shows the DECT LNA's gain and noise figure vs. frequency. The high reverse isolation of ~ 50 dB reduces the LO leakage to the antenna and simplifies the PCB design.

Conclusion

SiGe has provided a material engineering solution that allows for significantly improved transistor performance over conventional silicon transistor technology with similar processing complexity and line width requirements. By using standard Si wafers as well as largely standard production processes and equipment, SiGe provides an optimum cost/performance trade-off for many wireless applications.

This article has reviewed the capability of two SiGe processes for wireless applications: a low voltage IC process and a high voltage discrete process, and has included an analysis of the key figures of merit of the process and a discussion of the application of these parameters to circuits such as PAs and RF front ends. The stability and reliability of the SiGe process have been proven by extensive qualification testing as well as the performance of products in the field. With the cost structure of silicon processing, proven RF performance, high level integration ability and increasing acceptance of SiGe as a mainstream process, SiGe provides an optimal RF semiconductor choice for many wireless system applications.

References

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2.         E. Kasper, A. Gruhle and H. Kibbel, "High Speed SiGe-HBT with Very Low Base Sheet Resistivity," Technical Digest of the International Electron Device Meeting (IEDM), 1993, pp. 79-81.

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4.         A. Schüppen, U. Erben, A. Gruhle and U. König "Enhanced SiGe Heterojunction Bipolar Transistors," IEDM Technical Digest, 1995, pp. 743-746.

5.         E. Ohue, K. Oda, R. Hayami and K. Washio, "7.7-ps CML Using Selective-epitaxial SiGe HBTs," Proceedings of the Bipolar Circuits and Technologies Meeting, 1998, pp. 97-100.

6.         A. Schüppen, H. Dietrich, S. Gerlach, H. Höhnemann, J. Arndt and U. Seiler, "SiGe Technology and Components for Mobile Communications Systems," Proceedings of IEEE Bipolar/BiCMOS Circuits Technology Meeting, 1996, pp. 130-133.

7.         A. Schüppen, H. Dietrich, U. Seiler and H. von der Ropp, "A SiGe RF Technology for Mobile Communication Systems," Microwave Engineering Europe, June 1998, pp. 39-46.

8.         M. Bopp et al., "A DECT Transceiver Chip Set Using SiGe Technology," ISSCC '99 Digest, Vol. 42, Session 4, Paper MP4.2.