Adaptive Gate Bias Module Ensures Amplifier Performance

This compact circuit for solid-state RF power amplifiers provides the temperature compensation required to ensure optimum performance under varying temperature conditions as well as providing an optional windowed gate voltage for switching applications.

Temperature compensation is required to ensure that the quiescent current of an RF power amplifier remains nearly constant regardless of temperature variations caused by transistor self-heating. Without it, third-order intercept point (IP3), efficiency, and other characteristics are unpredictable and less than optimum. The effects of device heating and the necessity for providing temperature compensation to RF power transistors to ensure stable performance is widely documented¹ as are the causes of changes in quiescent current by the transistor’s variations in performance.² Consequently, temperature compensation has become an essential component in virtually all RF power amplifiers regardless of what type of device technologies are employed.

The adaptive bias circuit described in this article compensates for fluctuations in temperature and automatically adjusts the transistor’s gate voltage under varying temperature conditions. It can also provide a windowed gate voltage for switching applications. The circuit is compact, adds little to amplifier size and uses inexpensive devices. Although Freescale’s MRFE6VP5150N LDMOS transistor is used as an example, the circuit can be used with a broad range of LDMOS transistors and devices based on other technologies.

GENERAL CONSIDERATIONS

The active bias module described in this article (see Figure 1) provides this capability for an LDMOS RF power transistor. The level of compensation required varies with device technology and its class of operation, and is measured in mV/°C. To apply the proper compensation slope, either the device’s required gate-voltage compensation rate is found on its datasheet (see Figure 2) or its quiescent current drift is measured before designing a temperature-compensating circuit.

There are several techniques used to create temperature-compensating circuits, some of which employ temperature-sensing components such as thermistors, diodes or transistors. Other approaches employ microcontroller-based “lookup” systems³ in which stored values are used to vary gate voltages at measured drift rates.

When sensing temperature, the sensing component must be placed as close as possible to the transistor case.⁴ If applied externally it will be far from the transistor die, introducing a thermal time constant proportional to the change of case temperature (T_c) to junction temperature (T_j). The use of a microcontroller, while seemingly more sophisticated, requires as much if not more initial measurement effort with little additional benefit.

Production variation must also be considered as it can be as great as 200 mV. Even when operating in the less-demanding Class AB, a variation of 1 mV translates to a change of 1 mA; so, when using a lookup table, an encoded equation to adjust the value of starting gate voltage may not be useful.

When using external thermal-sensing components, accurate and repeatable measurements and calibration are essential before the circuit is finalized, as uncontrolled ambient temperature can cause fluctuations in voltage until a steady state is reached. This is even more important when the desired quiescent current is set very high, i.e., 2 to 3 A or more, because of the increased change in current vs. gate voltage during a 1 to 2 percent drift.

CIRCUIT DESIGN

The equivalent schematic for the adaptive bias module with test points is shown in Figure 3. The temperature-compensation circuit consists of a temperature sensing NPN bipolar junction transistor (BJT) U2 (in this case a BCW72LT1G from ON Semiconductor), its biasing network and voltage regulation. The voltage regulator U1 supplies +5 VDC and a reference voltage at Pin 4.

Pin 4 of U1 is normally a ground pin, but in this circuit the BJT base and collector are connected at Pin 4 to activate the tracking. If the pin were grounded, U1 would act as regulator as described on its datasheet. The supplied voltage is chosen to ensure that the BJT operates in its active-linear mode and that its base and collector currents scale to ensure predictable behavior.

Active Linear Region:

Regardless of the chosen sensing transistor, the BJT datasheet will show a characteristic curve of temperature coefficient (θ_BE) vs. collector current (I_C). From this curve the compensation slope in mV/°C is set to match that of the LDMOS transistor to ensure that the gate voltage correction results in the least possible deviation in circuit performance.

The BJT temperature coefficient curve shows only a small range of correction slopes may be achievable, which is complicated by the fact that the circuit may not be the same one that the manufacturer used to conduct the test. In addition, as the manufacturer’s test circuit and printed circuit board material differ from those used in the adaptive bias module, a new graph must be created.

The resistor divider consisting of resistors R6 and R7 is used to bias the BJT within its active-linear region. The resultant values for base and collector current are then predicted using a combination of measured and calculated values.

This assumes room temperature operation of 25°C. Note that β is equal to 310 at 25°C for the example values of R6=1200 ohms and R7=9090 ohms. The value of β will vary with the values chosen for R6 and R7, and will also vary slightly with temperature. Before accepting the temperature coefficient values in a BJT datasheet, it is important to determine that the slope θ_BE is valid for the given values of I_C. For the module described in this article, the curve was created using empirical measurements. The graph in Figure 4 can be used to determine the value of R7 when the value of R6 is 1200 ohms.

The plot in Figure 2 shows varying gate voltage versus normalized quiescent current as a function of temperature for the MRFE6VP5150N RF power transistor. The resulting slope vs. temperature for each class of operation is listed in Table 1.

The value of R7 for the sensing BJT must be chosen to achieve a compensation slope θ_BE that matches the quiescent current drift of the LDMOS transistor for the desired class of operation (in this case, 100 mA). If the drift slope of the transistor is not already known, Equation 3 can be used. Its delta variables are measured values.

The compensation rate of the sensing BJT should track the apparent drift of the LDMOS transistor’s gate voltage vs. temperature:

Values for V_GS and V_C are in millivolts and the change in temperature is in ºC.

PHYSICAL CONFIGURATION

The bill of materials for the active bias module is shown in Table 2. Circuit board dimensions are 0.85"×0.56". The module is attached to the amplifier board through an 8-pin breakaway header. The board is intended to be mounted vertically but either straight-pin or 90º pin headers may be used to accommodate the application. Standoffs cannot be mechanically attached to the board in its current configuration.

Because all input and output connections are located on one side of the board, the module can also be adapted to differing circuit topologies with jumper wires. The active bias module includes all parts but the BJT and U2 which should be placed as close as possible to the desired temperature-sensing point. Tuning of the compensation slope may require a value of resistor R7 (and possibly R6, depending on the class of operation) to be changed.

The supply voltage to the module is +8 VDC. Other input voltages require a resistor to ground to ensure that about +8 VDC is applied to the input pin of U1. Varying the input voltage too widely may keep the sensing BJT from operating in its active linear mode, eliminating the advantage of its predictable behavior.

The pin-out diagram for the module is shown in Figure 5. Pins 1, 3 and 5 are ground pins connected through drill-plated via holes to the ground plane of the module. Pin 2 is the gate voltage output to the LDMOS transistor gate lead. Pin 4 is for an optional input signal from a pulse generator or equivalent power amplifier circuitry for the gate windowing. This is useful when optimizing performance in pulsed-amplifier applications.

Pins 6 and 7 are DC feed lines to the BJT sensing transistor’s base and collector located on a separate application board. The module should be placed close to the BJT so it can be connected using jumper wires, which should be as short as possible to minimize inductive effects. The emitter of the BJT should be placed as close to the LDMOS transistor as possible to minimize the thermal time constant.

Pin 8, the voltage input to U1, is set at +8 VDC. Although input voltage may vary, it should be maintained at about +8 VDC using a resistor divider, for which space is provided on the module. The pin-out diagrams for the analog switch and voltage regulator are shown in Figure 3.

TEST SETUP AND MEASUREMENTS

The basic test setup for recording delta values of voltage and temperature required to calculate the module compensation slope is shown in Figure 6. Minimum equipment includes a source of heat and cold, a DC power supply, a multimeter and the device to be tested. The accuracy of the voltmeter should be at least 1 mV. The same test setup may also be used to measure the transistor’s drift with the exception that quiescent current is measured in milliamperes rather than millivolts. Modification of the setup for transistor temperature coefficient measurement is shown in Figure 7.

Each test begins at a temperature of 25°C to record the normalized value. Sufficient time must lapse before a measurement is recorded to ensure that leveling has occurred. The plotted measurements should be linear in relation to each other. The wider the range of measured temperatures, the more accurate the reading.

At a setting of 100 mA quiescent current, the gate voltage drift of the MRFE6VP5150N was measured at 2.421 mV/C (see Figure 8), confirming within a few microamperes the value on its datasheet. Figure 8 also shows the change in voltage versus temperature needed to maintain the required 100 mA quiescent current.

The module was measured with three different ratio values to create the result shown in Figure 4. When R7 is 9090 ohms, the temperature coefficient is closest to the gate voltage drift exhibited by the MRFE6VP5150N transistor at a 100 mA bias setting. While not exactly the same, it is close enough to be used for test.

Table 3 shows the change in quiescent current vs. temperature using the adaptive bias module for compensation. The change from -10° to 70°C is 2 percent or less. Based on the normal drift rate measured of -2.421 mV/C of the power transistor, the quiescent current drift might be 50 percent or more over this range at a starting I_DQ of 100 mA without the benefit of the module. Although the drift rate is not zero, the gate voltage is compensated well enough so that the RF output of the transistor is minimally affected.

OPERATION

At first turn-on, the potentiometer VR1 (see Figure 3) should be turned completely clockwise (off) to ensure that the gate voltage supplied to the transistor during initial biasing is low enough to prevent transistor damage. The module’s output voltage can then be adjusted by turning the potentiometer adjustment screw counter-clockwise until the desired nominal quiescent current level and gate voltage are reached. In most applications, it is best to bias the transistor by first applying the drain voltage. Most RF transistor datasheets provide I-V curves that can be used to determine the gate voltage required for any class of operation.

The duty cycle, pulse width and period vary by application. Whenever a pulsed gate voltage is required it is usually because the power amplifier’s performance goals cannot be met with a pulsed RF signal alone. The active bias module will receive a TTL signal from a separate pulse generator circuit or instrument that the module then uses to supply voltage to the transistor gate via output Pin 2.

Synchronizing components are not provided by this module when RF power and gate voltage are windowed together. This can be achieved through external monitoring and manipulation. The inset of Figure 3 shows the binary states of analog switch U3. In a logic HI (+1.65 to +5.5 VDC), the input signal is on and the output voltage at module Pin 2 is windowed off. In logic LO, the input signal is off and the output gate voltage is constant, allowing the module to be used in either a windowed or constant-gate-voltage configuration. To turn the gate voltage off, the DC supply to Pin 8 of the module is removed or a digital input of constant HI (100 percent DC) is provided so that the gate voltage is turned off via the digital control.

Switching rise and fall times are affected by the C_gs value of the LDMOS RF power transistor, on-state resistance, and other factors, which can be compensated for by tuning the module for specific applications. Space is provided on the module to attach additional 0805 chip capacitors for decoupling.

A typical gate voltage output waveform is shown in Figure 9. The gate voltage pulse width is about 100 µs at a duty cycle of 12.5 percent. The waveform input is the opposite duty cycle because of the logic state reversal of the analog switch.

CONCLUSION

The adaptive bias module described in this article automatically adjusts the gate voltage of an LDMOS RF power transistor under varying temperature conditions and provides an optional windowed gate voltage for switching applications. It can compensate for fluctuations in temperature that would otherwise cause the RF power transistor to have unpredictable performance.

1. Freescale Semiconductor Application Note AN1643, 1998.
2. P. Horowitz and W. Hill, “The Art of Electronics,” Cambridge University Press, 1998, pp. 74.
3. L. Li, T. Liu, Y. Ye, Y. Zhang and J. Li, “Embedded ARM-Based Automatic Gate Bias Control System for LDMOS RF Power Amplifiers,” International Conference on Electronics, Communications and Control, September 2011, pp. 2636, 2639.
4. S. Chen and J. Yuan, “Adaptive Gate Bias for Power Amplifier Temperature Compensation,” IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 3, September 2011, pp. 442-449.