An AlGaAs/GaAs HBT PA-LNA Transceiver MMIC Chip for 1.9 GHz PHS Digital Cordless Telephones

An AlGaAs/GaAs HBT PA-LNA Transceiver MMIC Chip for 1.9 GHz PHS Digital Cordless Telephones

The first results of a GaAs heterojunction bipolar transistor (HBT) power amplifier (PA)-low noise amplifier (LNA) integrated MMIC transceiver, developed for the Japanese 1.9 GHz personal handyphone system (PHS) digital cordless telephone, are reported. The MMIC is fully operational from a single 3.3 V supply including a digitally controlled DC power-down capability, and was evaluated in a 16-lead PSOP package with integrated ground slug and matched on a PCB using low cost resistors, capacitors and inductors. The two-stage PA provides a gain of 24.4 dB and a linear output power of 21.8 dBm with an adjacent-channel power (ACP) of –52 dBc at +/-600 kHz offset, which satisfies the PHS specifications. The HBT transmit/receive (T/R) MMIC achieves a linear power-added efficiency (PAE) of 31 percent that is comparable to previously reported PA-LNA MMIC transceivers based on GaAs FET technology but is four- to seven-times smaller in area.1,2 The HBT LNA provides 12.8 dB gain, a noise figure of 1.6 dB and a third-order intercept point (IP3) of 12 dBm while consuming less than 7 mA of bias current. The LNA and PA can be powered down with less than 10 mA of standby current without relying on a negative supply. This performance is believed to be among the best plastic-packaged results of an integrated PA-LNA transceiver MMIC developed for the 1.9 GHz PHS.

Kevin W. Kobayashi
TRW Electronic Systems and Technology Division
Redondo Beach, CA

GaAs HBTs are considered an attractive technology for commercial wireless applications, especially for the design of high efficiency, portable telephone transmitters. With more than 29 million GaAs HBT commercial MMICs delivered to date (approximate TRW actual chip deliveries), this technology has found its place in portable digital and analog telephones as well as fiber-optic telecommunication systems where approximately 90 percent of the HBT chip sales have been attributed to portable wireless telephone applications. GaAs HBTs offer many practical benefits for the wireless telephone, in addition to their well-known high power efficiency and linearity characteristics. These benefits include a single-supply bias, ultra-low idle current and power-down capability, and can mean more to the telephone manufacturer than power efficiency performance. For example, the monolithic single-supply operation and power-down (disable) capabilities eliminate the need for equivalent off-chip peripheral components and can result in a lower overall implementation cost for the telephone manufacturer. In addition, the HBT's low idle current increases battery life and provides longer talk time for the consumer. However, in future digital telephone applications, providing high linear efficiency will become increasingly important as the battery supply voltage is reduced. HBTs are well suited to meet these RF front end performance demands in addition to providing the practical implementation benefits mentioned previously. An example application that can take advantage of the HBT's high linearity performance and practical features as well as its existing high yield semiconductor manufacturing technology is the portable digital handset used in the Japanese PHS.

The RF front end of the 1.9 GHz PHS digital cordless telephone requires PAs with high linear efficiency, and LNAs with lower than 2 dB noise figure and high IP3 per unit bias current. The technical challenge is to integrate the critical RF front end PA and LNA on a single RFIC while maintaining performance in a high volume, low cost plastic package implementation. Figure 1 shows reported PAEs (1.9 GHz, ACP less than –50 dBc at +/-600 kHz) of devices, MMICs, and production-packaged PA and transceiver designs targeted for PHS. Current state-of-the-art high linear efficiency power FETs and HBTs have benchmarked record linear (ACP less than –50 dBc) efficiencies of 40 to 50 percent based on ideal device load-pull characterization and/or the use of active device linearization techniques.^4–6 As the product design progresses from device technology research benchmarks to practical multistage PA and T/R designs using high Q-factor multichip module (MCM)/ceramic or low cost packaged/PCB design-matching environments, the reported linear PAEs decrease to 30 to 40 percent.^7–12 This degradation in performance is due, in part, to the additional DC power of the integrated PA-driver stages as well as the practical employment of lower Q-factor components and substrates typically used in high volume commercial wireless telephones.

The push toward higher complexity T/R RFICs that integrate multiple RF front end functions as well as power-down and biasing circuitry is accompanied by the requirement of larger packages with greater pin counts. These higher complexity designs must absorb larger bond-wire parasitics and package/discrete matching component losses, which produce lower PAEs of 25 to 38 percent.^1–3 In this article, the first packaged results of an integrated HBT PA-LNA T/R MMIC that obtains 31 percent PAE while meeting the PHS ACP requirements are reported. The HBT T/R MMIC achieves PA PAE and LNA noise figure comparable to previously reported GaAs FET PA-LNA transceiver MMICs designed for 1.9 GHz PHS telephone applications while offering a chip size that is four- to seven-times smaller, lower idle current and practical implementation benefits.

The Packaged GaAs HBT PA-LNA Transceiver
The GaAs HBT PA-LNA transceiver MMIC developed for the PHS application was employed in a 16-lead PSOP package, as shown in Figure 2 . A ground slug is integrated into the bottom of the package to provide a low electrically inductive and thermally resistive path to ground. This configuration ensures electrical stability and good thermal heat sinking for the HBT PA. The GaAs MMIC integrates a single-stage L-C matched LNA and a two-stage PA as well as power-down circuitry. The PA relies on off-chip PCB matching using inexpensive commercially available discrete resistors and capacitors for both the input and output. The wirebond and package pin-lead inductances are incorporated into the matching circuits of both the PA and LNA matching. Inductances external to the package are provided by narrow PCB microstrip lines, but are used minimally. Interstage matching for the PA is achieved using monolithic capacitors and spiral inductors. Because the PHS telephone employs p /4-shifted quadrature phase-shift keying (QPSK) digital modulation and time-division multiple access (TDMA), the PA-LNA transceiver must provide high linear PAE in addition to low idle current in standby mode to maximize the battery life and talk time of the portable telephone. GaAs HBTs satisfy both these requirements effectively while also offering 3.3 V single-supply operation and monolithic power enable and disable capabilities that are necessary for TDMA operation. These features can reduce implementation costs significantly compared to FET technology solutions due to the elimination of negative voltage generators and external drain switches for power disabling.

The GaAs HBT LNA Design
Figure 3 shows a schematic of the HBT LNA. This LNA topology uses a combination of emitter feedback inductance L_e and a series base inductance L_b to optimize noise figure and the 50 W input match at 1.9 GHz.¹³ An HBT with four 2 x 20 mm2 emitter fingers was chosen based on examination of the device noise figure NF_min and gamma optimum characteristics in a current range that could amply meet the PHS IP3 requirements. A large emitter area was chosen for its low thermal noise contributions due to its small R_b and R_e , as well as its close gamma optimum match to 50 W , which eliminated the need for large spiral inductor values L_b and L_e .

Minimizing the value of these spiral inductors not only saves semiconductor real estate and cost, but also enables a lower practical minimum noise figure due to the absence of spiral conductor loss.¹⁴ The series package lead and wirebond inductances at the input and output of the LNA are also incorporated into the LNA design, and further reduce the number of turns required of the spiral inductors.

HBT noise figure performance trade-offs between bias, frequency and gamma optimum match have been discussed previously in detail.14 The single-stage HBT LNA had a simulated gain of greater than 12 dB, a noise figure of 1.3 to 1.4 dB and an IP3 of approximately 12 dBm at 1.9 GHz while consuming 6.5 mA. The amplifier operates from a 3.3 V supply and has monolithic power-down (disable) circuitry to shut off the LNA when the telephone is not receiving. The total idle current in this mode is much less than 1 mA. This low idle current is important for preserving the battery life, especially since the telephone is only receiving or transmitting one-eighth of the time and is in the idle mode three-fourths of the time it is in operation.

The GaAs HBT PA Design
Figure 4 shows the circuit schematic of the two-stage HBT linear PA. The PA consists of a feedback driver stage followed by an output stage. The driver stage is biased in class A mode while the output stage is biased in class AB mode to obtain good linear efficiency performance. The first stage employs light parallel resistive feedback to achieve stable gain at 1.9 GHz. It uses eight 2 x 10 m m2 HBT emitter fingers in parallel that have a total bias current of 36 mA under RF drive. This current level corresponds to a maximum current density of approximately 22.5 kA/cm² , which is conservative compared to the current densities used in the HBT reliability life tests that projected IC lifetimes of greater than 10⁷ hours at 125°C.¹⁵ Furthermore, the estimated junction temperature rise of the driver stage due to self heating is less than 20°C. The driver stage HBTs have been identified as the hot transistors on the chip since the output stage was designed more conservatively for power handling with thermal considerations in mind, while the first-stage device periphery was chosen to be relatively smaller for stable gain.

The first stage employs off-chip input matching, which comprises the series wirebond and lead inductance of the package and a couple of discrete capacitors mounted on a PCB. The output of the driver stage is matched monolithically to the input of the HBT output stage using spiral inductors and metal-insulator-metal capacitors. A parasitic package inductance on the driver's V_cc DC supply line also comprises part of this interstage matching. The PA stage comprises 64 2 x 10 m m² HBT emitter fingers in parallel comprising a total of 1280 m m² of effective emitter area. This stage is DC biased with approximately 110 mA of total current under RF drive and corresponds to a conservative current density of only 8.5 kA/cm² . The device output stage periphery was chosen to comfortably accommodate the Digital European Cordless Telecommunications (DECT) telephone specification, which requires approximately twice this current to deliver the needed saturated output power of 25 to 26 dBm. The output state is matched off chip for maximum power by incorporating the series package lead and wirebond inductances with external discrete capacitors mounted on the PCB. The output network of the PA is matched for maximum fundamental output power and also employs a second harmonic trap to improve linear performance.

Simulations of the two-stage linear PA predicted a PAE of approximately 35 percent at a 1 dB compression point (P1dB) of 23 dBm. The simulated power gain was 26 dB under the low bias current condition given previously. Under high bias conditions, saturated output power as high as 25 to 26 dBm and associated PAEs greater than 55 percent were obtainable with the same output power matching circuit tuned at the lower bias condition. Libra™ harmonic balance simulations simulated these results using a bipolar junction transistor (BJT) Spice macro model, which has been developed to model the HBT DC and RF characteristics.¹⁶ ACP simulations were not used in the original design.

Power-down bias circuits also are integrated onto the HBT MMIC, providing a convenient way to disable the DC power of the PA digitally. The idle currents were much less than 10 mA when the PA was switched off through the power-down ports. The fact that the amplifier can be powered on and off using a single positive supply and conventional control logic makes the HBT PA solution attractive for telephone manufacturers.

The GaAs HBT PA-LNA MMIC Chip
The 1.9 GHz PHS GaAs HBT transceiver MMIC is shown in Figure 5 . This MMIC is based on TRW's 2 mm GaAs HBT production process, which produces conservative f_T s and f_max s of 23 and 50 GHz, respectively. The total chip real estate is 0.9 x 1 mm² . The chip area is dominated by the 14 input/output bonding pads and the five spiral inductors that were used for interstage PA and LNA low noise matching. Even with the use of MMIC spiral inductors, the chip is comfortably four- to seven-times smaller than a PHS MESFET (PA-LNA) MMIC design, which is 2.5 x 2.5 mm² in area and incorporates a monolithic negative voltage generator.^1,2

The advantage of a GaAs HBT is that it can provide single-supply operation and power-down capability while maintaining a small MMIC size to keep the overall costs competitive. In general, HBT MMIC implementations are smaller due to their higher current and power-handling capability per unit area, which have made them an affordable alternative to other technologies.

The Packaged GaAs HBT PA-LNA Transceiver Performance
The GaAs HBT PA-LNA transceiver MMIC was packaged and matched on a PCB using commercially available discrete capacitors and resistors. Narrow microstrip traces were used to provide inductive matching as well. The PA-LNA chip was operated at a nominal supply voltage of 3.3 V for these measurements. The supply voltage was pulsed at a duty cycle that emulates the PHS TDMA burst-mode operation. This operating condition was intended to simulate the thermal conditions that the GaAs HBT PA-LNA MMIC will experience under typical telephone operation. The input of the HBT PA was matched for maximum gain while the output was tuned for output power starting with the optimized simulated values. The final tuned values were close to the original simulations. The PA was characterized for output power, gain and efficiency under an ACP of less than –50 dBc at 600 kHz offset from the carrier. The measured fundamental output characteristics (P_out vs. P_in ) of the two-stage GaAs HBT PA are shown in Figure 6 . For an ACP leakage of –52 dBc at +/-600 kHz, a linear PAE of 31 percent was achieved with an output power of 21.8 dBm. The output power requirement for the PHS digital telephone is 80 mW (19 dBm) at the antenna with an ACP of less than –50 dBc at 600 kHz offset from the carrier. The linear gain of the PA is 24.4 dB. Figure 7 shows the ACP leakage measurement of the HBT PA under the p /4-shifted QPSK modulation. One trace indicates the 21.8 dBm power integrated over a 300 kHz center bandwidth; the other trace illustrates the +600 kHz ACP of –30 dBm integrated over the adjacent-channel bandwidth. This performance meets the PHS ACP requirements. The alternate-channel power leakage suppression was measured to be less than –58 dBc at 900 kHz offset, which also meets the PHS requirement.

Figure 8 shows the broadband HBT LNA performance at a bias current of 7 mA and supply voltage of 3.3 V. The noise figure at 1.9 GHz is 1.6 dB with an associated gain of 12.8 dB. The measured noise figure is approximately 0.3 dB higher than the simulated value due to the excessive wirebond lengths in series with the input of the MMIC LNA, which prevented it from achieving its gamma optimum noise match. A noise figure improvement of 0.3 dB is expected by reducing the monolithic spiral inductance on the MMIC. This performance was obtained under a bias of 6.5 to 7 mA using a 3.3 V supply. Under this same bias condition, the two-tone output IP3 was measured to be 12 dBm and is adequate for the PHS application.

Table 1 lists the PHS specifications and the packaged GaAs HBT transceiver performance. The PA achieves 24.4 dB gain with a linear output power of 21.8 dBm while meeting the PHS ACP requirements. The linear PAE is 31 percent and is viewed as a conservative number since it reflects the performance for optimally tuned output power and not ACP or efficiency. PAEs as high as 40 percent are expected using ACP and efficiency load-pull matching or linearization techniques. However, the 31 percent linear efficiency achieved here compared favorably with commercially available transceiver products targeted for these applications.

Future Low Supply Voltage Applications Using InP-based HBT Technology
The future trend for portable wireless applications is to reduce the battery voltage level for operation. However, it will be difficult for GaAs HBTs to maintain both performance and monolithic bias integration as the voltage is dropped below 2.7 V. Nevertheless, GaAs HBTs still will be able to operate from a V_cc supply voltage as low as 1.5 to 2 V and maintain their attractive efficiency performance, although an off-chip bias solution may be required such as those found commonly in commercial FET PAs. InP-based HBTs can provide an attractive alternative to GaAs-based HBTs for these future low voltage applications. InP-based HBTs can incorporate a low bandgap material such as InGaAs, which reduces the V_be turn-on voltage to as low as 0.5 to 0.6 V, and can be even lower than silicon-based BJTs. A comparison of the V_be turn-on characteristics of GaAs- and InP-based HBTs as well as silicon-based BJTs is shown in Figure 9 . In addition, InP-based HBTs offer higher thermal conductivity with a factor of approximately 1.5-times better heat sinking capability than GaAs substrates, and higher peak electron velocity, which allows higher performance under lower voltage conditions. Figure 10 shows the low voltage cutoff frequency performance of InP HBTs, illustrating f_T as a function of device V_ce voltage for several bias current densities. Note that an f_T of greater than 25 GHz can be maintained for a V_ce operating voltage of only 0.5 V. This performance is more than adequate for most wireless applications. Also, it should be noted that the cutoff frequency is not limited by current density in this operating region. This characteristic can translate into dense circuits with high performance in an affordable area.

InP HBTs also provide good RF power performance under low voltages. Figure 11 shows the output power and gain characteristics of an InP-HBT device that has been characterized at 1.9 GHz, the frequency common to both PHS and DECT applications. The HBT has four 1.5 x 30 m m² emitter fingers and is operated at a low supply of 2.7 V. The HBT achieves 18 dB of linear gain and an output power of 19 dBm with an associated PAE of 66 percent. These data demonstrate the good power efficiency that InP HBTs can provide at low voltages. Figure 12 shows TRW's actual and projected GaAs HBT chip sales along with projected InP HBT chip sales as the operating voltage of the portable handset decreases with time. Although InP-HBTs may face a challenging road ahead to meet the volumes required for this market, the market has an already-established GaAs HBT commercial infrastructure that it can build upon. That infrastructure was created by the demand for practical implementation in a cost-driven environment.

Conclusion
As the portable wireless telephone market progresses toward the use of higher complexity integrated RFICs and lower operating voltages, it becomes increasingly challenging to maintain performance. A GaAs HBT 1.9 GHz PA-LNA transceiver MMIC has been presented that meets the current PHS specifications while providing 3.3 V single-supply operation and monolithically integrated power disable/enable capability with idle currents less than 10 mA. This GaAs HBT product compares favorably in performance to FET-based PA-LNA MMICs reported previously and is several-times smaller, offsetting the semiconductor fabrication cost differential. As the portable handset operating voltage drops in the near future, InP HBTs appear to be a possible candidate to replace GaAs HBTs. InP HBTs offer lower supply voltage operation, better thermal conductivity and practical bias benefits. The key to its deployment is the use of existing fabrication capability set up to support GaAs HBT commercial technology.

Acknowledgment
The author would like to extend special thanks to Ed Fong and Bill Burdette for their PCB design and characterization; Bill Pratt of RFMD for his practical design and packaging discussions; and Bob Pinato, Duncan Smith, Aaron Oki, John Cowles and Li Yang for their marketing, product definition and technology discussions.

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