Active Doubly Balanced Mixers for CMDS RFIC's

Active Doubly Balanced Mixers for CMOS RFICs

Patrick J. Sullivan and Walter H. Ku University of California, San Diego, Department of Electrical and Computer Engineering La Jolla, CA

Bernard A. Xavier Hughes Network Systems San Diego, CA

As the gate length of standard CMOS processes decreases into the submicron region, RF performance is becoming possible with standard CMOS technology. The realization of a CMOS RF stage could allow a considerable increase in transceiver integration and a reduction in transceiver cost. Modern communication systems have stringent dynamic range requirements. A radio receiver's dynamic range is often limited by the first downconversion mixer. Mixer design forces many compromises between figures of merit such as conversion gain, LO power, linearity, noise figure (NF), port-to-port isolation and power dissipation. This article reviews FET mixer operation and discusses the measured performance of two active doubly balanced mixer topologies in CMOS technology. Some general comments pertaining to the feasibility of an all-CMOS radio receiver, and the process and circuit issues this technology presents are also included.

A FET Mixer Review

Single-transistor FET Mixers

The similarities between MOSFET and MESFET devices allow the designer to apply the extensive knowledge of MESFET mixers¹ to the design of MOSFET mixers. Three standard mixing modes exist for simple single-FET mixers: transconductance, drain and resistive. The typical bias points of these modes are shown in Figure 1 . The FET transconductance mixer operates by changing the gate-source voltage, which swings the FET from the saturation region into the cutoff region. The FET transconductance mixer usually is biased at the threshold voltage and operated with a 50 percent duty cycle, which results in maximum conversion gain.² The drain source voltage ideally is kept constant and should be large enough to ensure that the FET device never enters the linear region of operation. The FET drain mixer operates via a drain-fed LO, which modulates the drain-source voltage of the device. This voltage swings the FET from the linear region into the saturation region. A resistive FET mixer operates by modulating the channel resistance (resistance between source and drain) with a large LO signal while keeping the FET in the linear region of operation.3 The MOSFET channel is switched between fully depleted and fully inverted regions of operation. Thus, the channel resistance is either close to infinite or a low value determined by device dimensions. No drain-source bias is applied or desired to keep the FET in the linear region of operation, hence, the resistive mixer commonly is referred to as a passive mixer. Generally, the LO is applied at the gate along with a DC gate bias. Because the FET channel resistance is linear in this region of operation (VDS = 0), very low intermodulation results.³

Balanced Mixer Structures

For optimum mixer intermodulation performance, downconversion mixers usually have an LO short at the IF output. This LO short is particularly important for active mixers because the LO typically is an order of magnitude larger than the RF signal and the LO is often amplified in active mixers. Typically, a large LO signal at the IF output port leads to poor mixer intermodulation performance and can also cause compression in the first IF amplifier. A doubly balanced mixer structure provides a virtual ground for the LO signal at the output IF port and no special active or passive circuitry is required to provide this LO short. As transceiver integration is increased and passive off-chip filters are eliminated, extensive on-chip LO-RF and LO-IF isolation will be required to compensate for the reduced performance of on-chip filtering. Doubly balanced mixers have inherent port-to-port isolation. These mixers are fully differential, which aids in filtering common-mode digital clock noise, making the doubly balanced structure suitable for IC design.

CMOS Doubly Balanced Mixers

Two active doubly balanced CMOS mixer test circuits were fabricated in a standard CMOS process, including a Gilbert cell mixer4 and dual-gate mixer,⁵ as shown in Figures 2 and 3 , respectively. Common source output buffers were added to buffer the mixer load from the measuring device's 50 W impedance. The buffers provide a wideband impedance match, and their power gain was simulated to be -1 dB. High current use in the output buffer ensured that the measured compression point and conversion gain were dominated by the mixer structure and not the output buffer. Current consumption was controlled by current mirrors that regulated current to the mixers and output buffers. Each mixer had an active area of less than 300 X 300 mm² .

CMOS Technology

When comparing the performance of different CMOS technologies, the single most important figure of merit is the device's effective gate length. Although CMOS technologies usually are quoted in the literature as drawn gate length, the effective gate length can be as much as 0.4 mm smaller than the drawn gate length because of process-dependent parameters such as lateral straggling of the ion-implanted source and drain. Process parameters of interest for the CMOS process in which the test circuits were implemented include a minimum gate length (drawn) of 0.8 mm, effective gate length (L_eff ) of 0.45 mm, gate oxide thickness of 115 nm, two-layer metal and nwell process. To evaluate the high frequency performance of the CMOS process, on-wafer small-signal scattering (S)-parameter measurements were made. Test structures in a common source-substrate configuration were fabricated within the CMOS process for measurement with ground-signal-ground coplanar probe points. A salicide process and the physical layout of multiple gate fingers aided in reducing gate resistance. The gate fingers were connected on both sides of the device, which improved the MOSFET devices' high frequency performance. For the 0.8 mm drawn (0.45 mm Leff) n-channel metal-oxide semiconductor (NMOS) device, the unity-current-gain cutoff frequency ft was 16 GHz and the unity-power-gain cutoff frequency fmax was 28 GHz. These values were extrapolated from measured S-parameter data. The measurement was taken with a 2 V drain-to-source and 2 V gate-to-source applied bias. The measured ft and fmax are similar to other published results for NMOS devices fabricated using a standard CMOS process.⁶

The Gilbert Mixer

The Gilbert cell topology is used commonly as a multiplier,⁷ where both inputs must remain linear with respect to the output. When implementing a Gilbert cell multiplier, it is common to use predistortion to increase the linearity of the switching core (the LO input). A Gilbert cell can also realize a mixer, where only one input (the RF input) must remain linear with respect to the output (the IF output). When operating as a mixer, predistortion is never used. In fact, a very nonlinear stage is desired for the switching core (LO input). The doubly balanced Gilbert cell mixer converts a differential input voltage to a differential current using an emitter-coupled pair. The output current of the long-tailed pair feeds into the switching mixing core, which commutates the signal current. When driven by an ideal square wave, the Fourier series expansion of conversion gain of a commutating mixer is (2/pi)² , producing a conversion gain penalty of -3.9 dB. Typically, the Gilbert cell mixer compresses in the input transconductance stage due to the differential pair's limited large-signal handling capabilities. Emitter degeneration often is used to reduce the gain of the differential pair; this reduction affects the NF adversely, resulting in only a modest increase in dynamic range. Usually, the NF is reduced by the front-end gain provided by the input emitter-coupled pair. Therefore, a direct trade-off exists between NF and compression point. The switching core can be viewed as a doubly balanced common gate amplifier with respect to the RF signal. If minimum LO power is desired for the applications, it is best to bias the LO core at the FET threshold where the transconductance can be modulated over the widest range with the smallest amount of LO power. CMOS Gilbert cell mixers can be implemented with either P-channel current source loads or polysilicon resistor loads. The poor transconductance of P-channel devices results in physically large P-channel transistors. These devices have large shunt capacitances that attenuate high IF signals, resulting in reduced conversion gain. To alleviate this problem, Gilbert upconverters typically use polysilicon load resistors. Resistive loads limit the current available to the mixer due to the voltage drop across the resistors. In turn, this current limiting restricts the increase in third-order intercept point possible from increased current consumption with a fixed supply voltage.

The Dual-gate Mixer

The dual-gate FET mixer in both MESFET and MOSFET varieties is a well-known technique^8,9 used to realize conversion gain and a reasonable NF. The dual-gate device is simply a cascode connection of two single-gate FETs in series. The typical physical device layout is shown in Figure 4 . This configuration is well suited to CMOS since the drain and source of the two devices can be shared, thus reducing capacitance at this floating node since the same diffusion can be shared, which allows for a smaller diffusion area. The dual-gate structure also has the added advantage of isolated signal and LO ports, allowing separate matching and providing inherent LO-RF isolation. Single-ended dual-gate mixers often are the mixers of choice in low power/low cost front-end designs.¹⁰ For MESFET dual-gate mixers, it has been established^1,6 that the optimum mode of operation is for the LO to be fed into the top gate and the signal to be fed into the lower gate. The applied LO signal modulates the floating node voltage. The modulated floating node is the drain of the lower FET, causing mixing action to occur in the lower FET (identical to a drain mixer). The lower FET gate source voltage is approximately constant and the modulated drain voltage swings the FET in and out of the linear and saturated regions over the LO cycle. Frequency mixing occurs due to the modulated drain-to-source conductance (g_ds ) in the lower FET. The dual-gate mixer can be implemented as a doubly balanced structure, which increases port-to-port isolation and achieves an LO short at the IF port without recourse to passive components.

Measurements

The mixer ICs are fully packaged in plastic surface-mount packages (SSOP-24), which are soldered on standard fiberglass PCBs (FR4). Due to the large pin-to-pin inductive coupling of plastic surface-mount packages, careful attention was given to pin-out selection and PCB layout to maintain LO-RF/LO-IF isolation. Fifty ohm microstrip lines mated the narrow pitch package pins to SMA connectors. The RF, IF and LO signals were fed on and off the chip differentially into passive 180°, 3 dB hybrids. The RF input ports were primarily capacitive in nature due to the CMOS gate. From |S11| measurements it was estimated that a 10.5 nH series inductance was required for a narrowband reactive input match at the RF ports. The packaging parasitic of the plastic surface-mount package, lead frame and bond wire provided an estimated 3.5 nH series inductance. An additional 7 nH of series inductance was implemented on the PCB with surface-mount components. At the bias point and the range of LO power where the dual gate mixes most effectively, the gate-source capacitance changes by approximately 100 percent and only the time average component can be tuned out. Large-signal-dependent matching is difficult at best. Therefore, no LO match was implemented for the dual-gate mixer, resulting in a poor LO reflection coefficient that caused even higher required LO power for the dual gate compared to the matched LO ports of the Gilbert mixer. Tuning the LO port degraded the RF port match due to the drain-gate capacitance of the lower FET device and the fact that the LO signal must exist at the drain of the lower FET to induce mixing action. Ideally, in a Gilbert mixer, the LO signal at the drain of the differential pair is zero. The measured LO and signal powers have been corrected to compensate for the passive hybrids' insertion loss. No other correcting factors, such as board loss, have been included in the measurements. Thus, the conversion gain reported represents the power gain of the CMOS mixer and buffer combination (-1 dB simulated) together measured into a 50ohm system at both the input and output. The single-sideband (SSB) NF measurement was further corrected to compensate for the narrowband RF filter's insertion loss and was measured with a standard NF meter.

The Downconverter's Performance Comparison

A direct comparison of two different circuit implementations often is fraught with danger because many variables are present in the circuit design. For example, one variable is the current distribution between mixer and buffer stages. A slight change in current distribution could result in a large change in many of the mixer's figures of merit. The two CMOS mixers were tested as downconverters for a standard superheterodyne radio architecture with an RF of 1.9 GHz, LO frequency of 1.65 GHz and IF of 250 MHz. The dual-gate mixer was tested at a power supply of 3 V and its DC bias points were adjusted to optimize for conversion gain and NF. The experimentally determined optimum DC bias points for the dual-gate mixer resulted in the LO port being biased at 1.56 V and the RF port being biased at 1.46 V. These bias conditions resulted in the lower gate (RF input) of the dual structure being biased in the linear region. Conversion gain as a function of LO input power for the dual-gate mixer is shown in Figure 5 . The dual-gate mixer's minimum SSB NF of 13.6 dB occurred at the maximum conversion gain of +2 dB with a corresponding LO power of +6 dBm. Similarly, for the Gilbert mixer, when the conversion gain was maximized at a supply voltage of 2.7 V, the SSB NF was at a minimum (8.8 dB), as shown in Figure 6 . The general trend of maximum conversion gain occurring at minimum NF was true for all measurements. Three regions of mixer operation as a function of LO power can be inferred from the data. The first region is the low LO power region where a 1 dB increase in LO power produces a 1 dB improvement in conversion gain. Similarly, a 1 dB increase in LO power causes a 1 dB reduction in the SSB NF. The second region is the optimal LO power region, where both the conversion gain and NF are constant for a broad region of LO power. The third region of operation exists where the LO power overdrives the mixer, reducing conversion gain due to the subtracting nature of the LO power's third-order harmonic. The data imply that the dual-gate mixer requires larger LO power and achieves lower conversion gain than the Gilbert mixer due to the lower mixing efficiency of conductance g_ds modulation of a drain mixer. The dual-gate conductance modulation mixing has the advantage of lower intermodulation distortion. A plot of conversion gain and SSB NF as a function of supply current (V_DD = 2.7 V) for the Gilbert mixer is shown in Figure 7 . The NF had a broad minimum as a function of supply current while the conversion gain was dependent on the supply current. The optimum measured conversion gain is 5.5 dB with an associated SSB NF of 8.8 dB at a supply voltage of 2.7 V. The Gilbert cell doubly balanced mixer demonstrated more than 30 dB port-to-port isolation when driven by differential signals; the dual-gate circuit typically achieved 20 dB. The overall downconversion performance of the two mixers is listed in Table 1 . The Gilbert mixer has higher gain and a lower NF than the dual gate, while the dual gate has a larger input third-order intermodulation point (IIP₃ ), as expected.

The Gilbert Mixer's Upconverter Performance

The Gilbert mixer was also measured as an upconverter. The overall upconverting mixer performance with an RF output frequency of 2.4 GHz is listed in Table 2 .

The output spectrum was a double sideband with the LO carrier suppressed. Generally, the lower sideband was a few decibels higher than the upper sideband. Upconversion gain was measured while both the RF and LO signals were swept simultaneously to give upconversion gain as a function of RF output frequency with a fixed IF input frequency, as shown in Figure 8 . The data show an upconversion gain of 17 dB at an RF output frequency of 900 MHz and an upconversion gain of 12 dB at a frequency of 2.4 GHz. The upconversion gain as a function of RF followed a slope of -20 dB/decade characteristic of a single-pole RF system. The pole's resistance comprised the mixer load resistance in parallel with the mixer core's output conductance, while the capacitance comprised the source follower buffer FET's gate capacitance and the mixer core's drain substrate capacitance. The mixer's unity gain crossover frequency was 5 GHz. The LO-RF isolation of an upconverter is especially important since, in general, the LO frequency is close to the desired RF signal and thus is difficult to filter. Due to intermodulation requirements, the LO power typically is an order of magnitude larger than the IF input, thereby compounding the problem. For LO frequencies below 3 GHz, the doubly balanced upconverter exhibits LO-RF/LO-IF isolation in excess of 30 dB with as much as 40 dB at certain frequencies. For LO frequencies in the 3 to 5 GHz range, the LO-RF/LO-IF isolation was better than 25 dB. To examine the mixer's LO power requirement, the conversion gain was measured at an RF output frequency of 2.4 GHz while sweeping LO power. A peak conversion gain of 12 dB was achieved with +3 dBm LO power. Reducing the LO power to -7 dBm produced a modest reduction in conversion gain to 10 dB, as shown in Figure 9 .

Comments on RF CMOS

Both silicon CMOS and bipolar technologies can operate at commercial wireless frequencies such as 1.9 GHz for the personal handyphone system. However, silicon bipolar devices have substantial advantages in terms of impedance matching, device matching and superior g_m /I ratios (transconductance per unit of current) over CMOS technology available currently. Due to the capacitive input impedance of a MOSFET gate, matching is more difficult when compared to the base of a bipolar device, which is closer to 50ohm. Matching the MOSFET device requires a high Q inductor, which suggests that CMOS low noise amplifier mixers will be more difficult to manufacture. Process variations in CMOS are larger than bipolar technology, resulting in large device-to-device mismatching and wafer-to-wafer variance. These variations in CMOS technology are due mainly to the process variations in gate oxide thickness compared to bipolar technology, which achieves tight control over the growth of the base region by diffusion. These CMOS process variations translate into device offsets that reduce the achievable image rejection of complex mixers and produce lower port-to-port isolation. However, the mixers presented in this article achieved 30 dB port-to-port isolation, which is comparable to (if not better than) other technologies. Note that only a handful of mixers were measured as opposed to the tens of thousands of circuit measurements required for production qualification. When compared to bipolar technology, the poor g_m /I ratio of CMOS implies that an RF CMOS front end would produce an increased current consumption compared to a bipolar RF front end. Current consumption is a major factor in wireless transceiver design. FET devices in both MESFET and MOSFET technologies generally produce less intermodulation and cross-modulation distortion than bipolar devices because, to a first-order approximation, FET current depends quadratically on gate-source voltage while bipolar current depends exponentially on the base-emitter voltage. As a result, FET technology is often preferred to bipolar devices in mixers because the lower intermodulation can result in larger dynamic range. Deep submicron FETs do not inherit the long channel quadratic relationship, which produces increasing intermodulation distortion but also allows higher operation frequencies and slightly lower NF due to higher f_t and f_max . The possibility of increasing transceiver integration by integrating a CMOS baseband stage and a CMOS RF stage is attractive from a cost viewpoint. However, this step will be difficult to achieve because of the interference between baseband and RF. Digital clock spurious tones will mix with the RF LO signals to produce receiver desensitization. Digital circuits are not differential; the digital supply pins' ground bounce will provide a convenient radiation path to the RF circuitry via the chip bond wires. With a conventional superheterodyne architecture, a single-chip transceiver would have difficulty achieving a frequency plan with the required separation. In addition, packaging limitations would restrict channel selectivity because the out-of-band rejection of off-chip surface acoustic wave filters would be limited by package pin-to-pin isolation. Other architectures, such as direct conversion or near-zero IF, could be employed. However, the high 1/f noise characteristics of CMOS may limit sensitivity. The device mismatch will limit the achievable IQ channel crosstalk and produce higher DC offsets than a bipolar receiver.

Conclusion

Two fully integrated doubly balanced CMOS mixers have demonstrated the ability of a standard CMOS process to operate at commercial wireless frequency bands with reasonable dynamic range. As a downconverter, the dual-gate mixer demonstrated an IIP3 of 0 dB and an SSB NF of 13.6 dB; and the Gilbert mixer demonstrated an IIP3 of -3 dB and an SSB NF of 8.5 dB. The dynamic range and port-to-port isolation make doubly balanced CMOS mixers suitable for downconverter and upconverter applications in an all-CMOS transceiver. It should be noted that the performance of a CMOS Gilbert cell mixer implemented in a complete CMOS RFIC transceiver would be lower than the measured performance of this mixer. It is difficult to generate ideal differential RF and LO signals on chip, and on-chip inductors exhibit low Q factors, producing poorer on-chip matching. Silicon bipolar technology has substantial advantages in terms of impedance matching, device matching and superior gm/I ratios over CMOS technology available currently. The continuing miniaturization of CMOS technology will improve RF CMOS performance. Currently, RF CMOS is a highly active research area, and integrated CMOS transceivers¹¹ and receivers¹² are demonstrating promising results. Using CMOS technology, RF designers can utilize the large infrastructure in place that supports and develops low cost, mass-produced ICs. The drive to increase transceiver integration and reduce transceiver cost makes CMOS an attractive technology for low cost, highly integrated transceivers.

References

1. S.A. Maas, Microwave Mixers, Artech House Inc., Norwood, MA, 1993.

2. R.A. Pucel, D. Masse and R. Bera, "Performance of a GaAs MESFET Mixer at X-band, IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-24, June 1976, pp. 351-360.

3. S.A. Maas, "A GaAs MESFET Mixer with Very Low Intermodulation," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-35, Apr. 1987, pp. 425-429. 4. P.J. Sullivan, B.A. Xavier and W.H. Ku, "Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer," IEEE Journal of Solid-state Circuits, July 1997.

5. P.J. Sullivan, B.A. Xavier and W.H. Ku, "A 1.9 GHz Double-balanced, Dual-gate Downconversion Mixer in 0.8 mm CMOS," IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications Proceedings, Feb. 1997.

6. S.P. Voinigescu, S.W. Tarasewicz, T. MacElwee and J. Ilowski, "An Assessment of State-of-the-art 0.5 mm Bulk CMOS Technology for RF Applications," International Electron Device Meeting Proceedings, Dec. 1995, pp. 721-724.

7. B. Gilbert, "A Precise Four-quadrant Multiplier with Subnanosecond Response," IEEE Journal of Solid-state Circuits, Dec. 1968, pp. 365-373.

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9. S. Weaver, "TV Design Considerations Using High Gain Dual-gate MOSFETs," IEEE Transaction on Broadcast and Television Receivers, Vol. BTR-19, No. 2, May 1973, pp. 87-98.

10. V. Nair, S. Tehrani, R.L. Vatkus and D.G. Scheitlin, "Low Power HFET Downconverter MMICs for Wireless Communication Applications," IEEE Transactions on Microwave Theory and Techniques, Vol. 43, No. 12, Dec. 1995.

11. A.A. Abidi, "CMOS-only RF and Baseband Circuits for a Monolithic 900 MHz Wireless Transceiver," IEEE Bipolar Circuits Technology Meeting Proceedings, Sept. 1996, pp. 35-42.

12. J.C. Rudell et al., "A 1.9 GHz Wideband IF Double-conversion CMOS Integrated Receiver for Cordless Telephone Applications," IEEE International Solid-state Circuits Conference Proceedings, Feb. 1997, pp. 304-305.

Patrick J. Sullivan is a PhD candidate in electrical and computer engineering at the University of California, San Diego. He has designed RFICs for Pacific Communication Sciences Inc. and Rockwell Semiconductor Systems.

Walter H. Ku received his BS degree (with honors) from the Moore School of Electrical Engineering, University of Pennsylvania, Philadelphia, PA, and his MS and PhD degrees from the Polytechnic Institute of Brooklyn, NY. Over the years, he has served as a consultant to the Department of Defense. Since September 1985, Ku has been a professor of electrical and computer engineering at the University of California, San Diego. He is also the founding director of the NSF I/UC Research Center on Ultra-high Speed Integrated Circuits and Systems.

Bernard A. Xavier received a first-class honors degree from Kingston Polytechnic, UK, in 1989. He then began work at Texas Instruments, UK, and later studied for his PhD degree at Brunel University, UK. Currently, Xavier is employed in the US at Hughes Network Systems.