This article presents an efficiency improvement method for RF power amplifiers, using an integrated digitally-controlled dynamic bias switching (DDBS) circuit. The DDBS IC dynamically selects two different drain bias voltages for the power amplifier, using its switching stage according to the limited envelope signal. To maximize the efficiency improvement, the optimum threshold voltage and bias levels were determined after analytic consideration for the statistical distribution of the envelope signal. For verification, a DDBS IC was designed and fabricated using a 0.18 µmCMOS process. The fabricated DDBS IC was evaluated using an OFDM signal, which has a center frequency of 2.6 GHz, a bandwidth of 9.4 MHz and a PAPR of 9.6 dB. The DDBS IC considerably increases the power amplifier’s PAE from 21.3 to 32.2 percent, at an average output power level of 25 dBm, while good linearity performance with an EVM of less than 4 percent is maintained.

Modern wireless communication systems utilize spectrally efficient modulation methods, such as orthogonal frequency-division multiplexing (OFDM) signals. These modulated signals have a wide bandwidth and high peak-to-average power ratio (PAPR or PAR) for a higher data rate. The signals with high PAPR cause the power amplifier (PA) to have low average efficiency because the PA should be operated in output back-off. A low efficiency of the PA means that the battery life is shorter.^1-3

Various researches have been carried out to improve the average efficiency of the PA.^3-15 Especially, bias modulation methods for the drain or collector are very straightforward and effective.⁴ Envelope elimination and restoration (EER), hybrid-EER and envelope tracking (ET) techniques utilize a continuous envelope signal to control or modulate the drain or collector bias of the amplifier.^4-7 Continuously modulated drain/collector biases allow the PA to operate near to saturation, which is a high-efficiency region, according to the envelope level. Hence, the average efficiency can be improved. However, continuous drain/collector bias modulation techniques require a very high-speed DC-DC converter to modulate the bias voltage with the speed of the envelope signal. They generally have a complex structure and require a large off-chip inductor.^4-7

An alternative solution could be a discrete bias modulation technique, known as dynamic bias switching (DBS).^8-10 It has two or more different bias voltage levels, which can be dynamically supplied to the drain of the PA according to the envelope level. A low supply voltage is applied to the drain of the PA when the envelope signal is lower than the threshold voltage. When the input voltage exceeds the threshold voltage, a high supply voltage is instantly selected and is provided to the drain of the PA. The supply modulator for DBS consists of a simple switching circuit, which is much simpler than the high-speed DC-DC converter for the continuous bias modulation methods. Because of the higher operating speed of the simple switching circuits of the DBS, the supply modulator can be applied to wideband modulated signals. In addition, the binary control signal used to select the bias voltage can be made by a digital signal processing technique.

In this article, a CMOS digitally-controlled dynamic bias switching integrated circuit (DDBS IC) is presented to enhance the efficiency of power amplifiers. The designed DDBS IC has a very simple structure, which does not need the envelope detection circuit, envelope processing circuit and high-speed DC-DC converter. A two-level control signal for the high-speed bias switch in the DDBS IC is generated from the real-time envelope signal using a properly optimized threshold voltage. The high-speed bias switch dynamically selects the bias voltage between the lower and normal bias voltages according to the control signal. Because the threshold voltage and lower bias voltage are important for efficiency enhancement, they are analytically optimized.

The DDBS IC was fabricated using a 0.18 µm CMOS process and was evaluated using an OFDM signal in the 2.6 GHz band. It is applied to a commercial InGaP/GaAs HBT power amplifier, to validate its capability for performance improvement. The results were compared to the case without the DDBS IC.

Operation Principle of DDBS

An operation of the dynamic bias switching can be described as:

where v_DD(t) is an instantaneous drain bias voltage, which has one of the two DC voltages (V_DD,low and V_DD,high). V_ENV(t) and V_TH are instantaneous output envelope voltage and an output-referred threshold voltage, respectively. If the envelope is greater than V_TH, the PA has a drain bias voltage of V_DD,high. Otherwise, the bias voltage is instantly switched to V_DD,low.

Figure 1 describes the operation of the DDBS on an ideal Class B PA. The envelope signal for the modulated input voltage waveform is compared with the constant threshold voltage. For the envelope signal greater than the threshold voltage, the PA operates at point ‘A’ on the I-V plane and its voltage waveform is presented below the I-V curve. If the envelope level becomes lower than the threshold, the bias point instantly shifts to point ‘B’ so that the voltage waveform also shifts down. The efficiency can then be improved because the DC power consumption is reduced for an envelope signal lower than the threshold.

Figure 2 shows a schematic diagram of the power amplifier with a DDBS IC. From the digital I/Q signal, the envelope signal is extracted and is digitized using a digital comparator with a given threshold level. The two-level digitized signal is applied to the DDBS IC and is used to control the switch to select the bias voltage between V_DD,high and V_DD,low. The DDBS IC is very simple because the envelope signal is processed in the digital domain.

The DDBS IC consists of buffer stages, a switch driver, a PMOS switch and a diode. The buffer and switch driver stages are designed to have rail-to-rail output characteristics in order that the PMOS switch can be fully turned on or off. The size of the PMOS switch and diode should be large enough to drive the required current from the PA. The PMOS switch is designed in consideration of a trade-off between its frequency response and current handling capability. The diode is designed using a native NMOSFET, which has a very low turn-on threshold so that a voltage drop can be low over the diode.

According to the control signal, the voltage V_DD,high is supplied to the drain of the PA when the PMOS switch is turned on. The voltage V_DD,low is supplied through the diode when the PMOS switch is turned off. The input signal of the PA is the modulated RF signal of which the envelope signal should be accurately synchronized with the dynamic drain bias voltage in time using a time delay block.

One of the most important considerations in the DDBS system design is how to determine the threshold voltage and V_DD,low for the best efficiency improvement because V_DD,high is generally given by the system. In the next section, the effect of the threshold and V_DD,low on the efficiency of the DDBS system will be analyzed. The optimum values for both the threshold and V_DD,low will be found.

Operation Conditions

Efficiency of the Class B PA

The threshold voltage gives a reference to bisect and limit the envelope signal, and then composes a control signal for the DDBS IC. Because it is very important to determine the threshold voltage and V_DD,low for the performance optimization, they are analyzed based on the ideal Class B amplifier.

The fundamental output power is given by

where V_max and I_max are the peak amplitudes of the output voltage and current, respectively. v is a normalized envelope voltage. Thus, v² is an output power back-off and is defined as P_out/P_max, where P_max is V_maxI_max/4. The DC power consumption is then given by

Hence, the drain efficiency becomes:

With no output power back-off, where v = 1, the ideal Class B PA has an efficiency of 78.5 percent. If the drain bias continuously varies according to the output power back-off level, the maximum efficiency will be maintained. This condition is given as:

For the continuous bias modulation methods, such as EER, hybrid EER and ET, Equation 5 is the ideal condition for the drain bias modulation. However, for the DDBS, a single value of V_DD,low with the threshold voltage should be selected for efficiency optimization.

Optimum V_DD,low and the Threshold Voltage

For the modulated signals such as OFDM, the average efficiency of the PA, rather than the peak efficiency, is meaningful, because the PA operates on a low or mid power region for the greater part of the time. Therefore, statistical distribution of the normalized envelope voltage should be considered to optimize the average efficiency. Figure 3 shows a probability density function (PDF) of the up-link OFDM signal based on the 64-quadrature amplitude modulation (64-QAM). Relatively high statistical distribution can be observed for the normalized envelope voltage between 0.1 and 0.5 V. Figure 3 also plots the drain efficiency of the ideal Class B amplifier.

For the time-varying envelope signals, the average efficiency can be defined as:

where p(v) is a probability density function of the envelope, P_out(v) is a fundamental output power and P_DC(v) is a DC power consumption. The knee voltage of the transistor was assumed to be zero.

The average efficiency of the DDBS system which has two different bias voltages can be expressed as:

V_DD,high is the same as V_max, due to the zero knee voltage. P_out,avg is an average output power. In order to avoid saturation in the low power region for the linear operation, the following condition should be satisfied:

Here, the maximum efficiency improvement can be achieved if the left and right sides of Equation 10 are the same.

Figure 4 presents the calculated relative average DC power consumption and an average efficiency according to the normalized threshold voltage which is V_TH/V_max. The calculation was done under the condition that V_TH is equal to V_DD,low for maximum efficiency improvement. If V_TH/V_max is 0, V_DD,low and its occurrence are 0 so that only V_DD,high is supplied to the drain of the PA. When V_TH/V_max is 1, V_DD,low should be the same with V_DD,high or V_max. Therefore, the drain bias has only V_DD,high all the time. For both cases, the average efficiencies are approximately 31 percent. The obtained optimum value of V_TH/V_max is approximately 0.52, which means that the V_DD,low is 0.52 times V_DD,high. The maximum average efficiency is almost 50 percent for the DDBS system.

For a more practical solution, the knee voltage of the transistor can be considered. It is linear with the drain to source voltage or drain current if a constant on-resistance is assumed. The voltage swing of the fundamental component is restricted by the knee voltage. Calculated efficiencies, with the knee voltages as a parameter, are plotted in Figure 5. A non-zero knee voltage degrades the average efficiency, but the optimum value of V_TH/ V_max is not changed, as shown.

Experimental Validation

The designed DDBS IC is fabricated using the TSMC’s 0.18 µm CMOS process, with the dimensions of 1×1 mm², including pads. Figure 6 shows a photograph of the implemented DDBS IC. To verify the feasibility of the DDBS system, the DDBS IC is applied to Anadigics’s AWT6261R, which is a PA for mobile WiMAX application, based on InGaP/GaAs HBT technology. Figure 7 shows the test setup for the overall DDBS system. The upper signal generator provides the DDBS IC with the real-time binary control signal, which is synchronized with the modulated RF signal from the lower signal generator. The binary control signal for the DDBS IC is generated by the PC. The RF modulated signal, which has a center frequency of 2.6 GHz, a bandwidth of 9.4 MHz and a PAPR of 9.6 dB, is applied to the PA.

Figure 8 presents the measured results of the DDBS IC with a load resistor of 30 Ω, which is connected to the switch rather than to a PA. Based on the envelope of the OFDM signal, the generated binary control signal is applied to the DDBS IC. V_DD,low and V_DD,high are 2.0 and 3.3 V, respectively. For this case, V_TH/V_max is approximately 0.45 because a knee voltage of 0.5 V is considered. The measured voltage drop of the diode is as small as 0.08 V.

Figure 9 shows the test results of the PA for various fixed drain voltages of 1.5, 2 and 3.3 V. The measured gain is 29.5 dB for the bias voltage of 3.3 V. Gain degradations of 0.6 and 1.6 dB are observed for the supply voltages of 2 and 1.5 V, respectively. The measured EVM performances are almost the same and are approximately 1.2 percent at an output power of 15 dBm. However, the EVM performance is quickly degraded as the output level increases. The lower bias voltage causes earlier degradation in EVM performance due to a signal clipping.

Figure 10 shows the measured PAE and EVM of the power amplifier with the DDBS IC. The measurements were carried out with two different V_DD,low voltages of 1.5 and 2 V and a fixed V_DD,high of 3.3 V. In order to compose a control signal for the bias switch, V_TH/V_max was experimentally refined from its initial value of 0.52 to 0.45 for the best trade-off between the efficiency and linearity of the DDBS system.

For the DDBS system with a very low V_DD,low of 1.5 V, a high PAE of 43.6 percent was achieved with a slightly degraded EVM of 8.4 percent at an average output power of 25 dBm. The degraded EVM could be improved using a digital predistortion technique. However, if the voltage level of V_DD,low is slightly increased, the additional circuit for linearity improvement such as digital predistorter is not required. The DDBS system with a V_DD,low of 2 V with V_TH/V_max of 0.45 has an increased PAE from 21.3 to 32.28 percent with a good linearity performance, that is an EVM of less than 4 percent, at an output power level of 25 dBm. These performances are compared to the representative previous works in Table 1.

Conclusion

In this article, an efficiency enhancement technique for the power amplifiers based on an DDBS IC is presented. Considering a statistical power distribution of the signal envelope, optimum operation condition of the system is analyzed for the threshold and bias conditions. To verify the performance, the DDBS IC was designed and implemented, using 0.18 µm CMOS technology. It was tested with an InGaP/GaAs HBT PA using the 2.6 GHz band up-link m-WiMAX signal.

The measured results show that a high improvement of PAE by 11 percent was achieved for the V_DD,low of 2 V with a good EVM performance of less than 4 percent at an output power level of 25 dBm. The DDBS system has a very simple circuit and provides an effective way to enhance the average efficiency of the PA for the signals having high PAPR.

Acknowledgment

This work was supported by the National Research Foundation of Korea Grant funded by the Korean Government (NRF-2011-220-D00084).

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