An Input Matching Network Without Gain Trade-Off for a CMOS LNA

A capacitive feedback circuit along with a π-matching network is proposed to achieve the input matching condition without gain trade-off for the common-source low noise amplifier (CSLNA). The π-matching network introduces an additional degree of design freedom and allows the LNA to achieve high gain. Designed for the 2.4 GHz ISM band, the proposed LNA achieves a measured gain of 21.5 dB with an S₁₁ of -12 dB while consuming only 0.6 mW. The NF is 4.9 dB and the IIP3 is -12 dBm.

Nowadays, it is normally desirable to have a high gain LNA in most wireless receivers. Serving as the first active block in the receiver chain, an LNA should provide enough gain to overcome the noise contribution of the subsequent stages and add as little noise as possible. However, in some wireless standards such as the IEEE 802.15.4, the LNA’s noise figure (NF) is not a critical performance parameter.^1,2 The NF requirement can be relaxed to allow optimization on other design parameters such as gain, power consumption and chip area. The LNA presented in this article is designed for the IEEE 802.15.4 standard.

Popular LNA topologies are the inductive source-degeneration common-source LNA (L-CSLNA), the common-gate LNA (CGLNA) and the resistive feedback LNA (RFLNA). The L-CSLNA is generally preferred for ultra-low power narrow-band applications due to its ease of input matching, high gain and low noise.^3-6 However, its gain performance is limited by the input matching condition. There exists a trade-off between high gain and good input matching in the L-CSLNA.

In this article, an LNA, where the input matching is realized by a capacitive feedback scheme and a π-matching network, is proposed. The capacitive feedback helps to reduce the number of inductors needed for input matching, when compared to the L-CSLNA. Moreover, higher gain and more degrees of design freedom are achieved with the use of the π-matching network. The concept of utilizing capacitive feedback for input matching has been implemented by Chung and Shahroury.⁷ However, the LNA used has a non-cascode structure. In order to have high reverse isolation, it makes use of a multi-stage structure, which results in very high power consumption. The proposed LNA has a single stage cascode structure. The detailed analysis on input matching, gain and NF are presented. The LNA was implemented using the IBM 0.13 μm R_f CMOS technology.

Inductive Source-degeneration Common-source LNA

The schematic of the L-CSLNA and its equivalent small signal circuit for input impedance analysis are shown in Figure 1. C_Y includes all parasitic capacitances at node Y and can be approximated as:

R_Y is the total impedance looking into the source of M₂ from node Y. In this circuit, R_Y can be approximated to be 1/g_m2 where g_m2 is the transconductance of transistor M₂. The L-CSLNA’s input impedance is derived to be:

where ω is the operating frequency, C_gs1 and C_gd1 are the parasitic gate-source and gate-drain capacitance and g_m1 is the transconductance of transistor M₁. When C_gd1 → 0, Z_{in_L} can be simplified to:

which is consistent with the classical result. At the resonant frequency, the input impedance, R_{in_L}, equals to g_m1L_s/C_gs1 and the transistor’s transconductance, g_m1, is effectively boosted to G_{eff_L}g_m1 where G_{eff_L} is:

and ω0 is the resonance frequency. The noise factor of this LNA at the input matching condition is:

In Equation 5, R_Lg is the parasitic series resistance of inductor L_g, R_g is the gate resistance of transistor M₁,  and  are the drain current noise of transistor M₁ and M₂, respectively, and  is the input source voltage noise. A large g_m1 and small C_gs1 are desired to achieve high gain and low noise.^4,5 Due to the input matching condition, the value of L_s is normally quite small. The requirement of small L_s sometimes becomes a nuisance for the LNA design, because not all the inductor values are available in the Process Design Kit (PDK).

The Proposed Capacitive Feedback CSLNA with P-matching Network

The LNA introduced by Cheng⁷ uses the parasitic gate-drain capacitance of the input device and the output capacitance, C_L, to form the capacitive feedback matching network. Only one inductor was used to realize the input matching. However, the analysis is only applicable for the non-cascode structure. For the CS topology, in order to have high reverse isolation and good stability, a cascode structure is preferred. Here, the analysis for the cascode structure is presented. Its schematic is shown in Figure 2. Based on the small signal circuit (b), the input network of the cascode capacitive feedback LNA can be converted to a series RLC matching network including of L_g, C_f and R_f. The value of C_f and R_f can be derived as:

C_x and R_x can be calculated as follows:

To achieve the input matching, R_f is designed to be equal to R_s. The effective gain of this input matching network is:

The noise factor at the input matching condition of this LNA can be derived as:

When compared to the L-CSLNA, the capacitive feedback LNA requires a lesser number of inductors for input matching. But this benefit comes with a trade-off of higher NF, which can be observed from Equations 5 and 11. As seen from Equations 4 and 10, the input network’s effective gain of the two LNAs discussed above are limited by the 50 Ω matching condition. To achieve a good input matching, R_f and (g_m1L_s/C_gs1) must be matched to 50 Ω. This will restrict the selection of G_{eff_L} and G_{eff_no_L}, therefore limiting the achievable gains of these two LNAs. There exists a trade-off between high gain and good input matching in these two LNAs.

The proposed LNA adds a parallel capacitor, C_g, preceding the gate inductor as seen in Figure 3 to create a π-matching network. It shows the small signal circuit for input impedance calculation of the proposed LNA (b). R_f and C_f are formed by the capacitive feedback mechanism as described above. Inductor L_g can be divided into two smaller parts: L₁ and L_f. These two inductors will resonate with C_g and C_f , respectively. The input impedance at the resonance frequency is:

The effective gain of the proposed input matching network is:

Equation 13 shows that the effective gain of the proposed LNA can be increased by reducing the value of R_f , unlike in the capacitive feedback LNA and the L-CSLNA, where the effective gains are limited by the 50 Ω matching condition. When reducing R_f , the input impedance of the LNA can be matched to 50 Ω by decreasing L₁ according to Equation 12. Capacitor C_g and inductor L₁ add an additional degree of freedom to the LNA design. The effective gain is no longer limited by the input matching condition. Therefore, the proposed LNA will be able to achieve much higher gain when compared to the L-CSLNA and the capacitive feedback LNA. Figure 4 shows the S₂₁ and S₁₁ responses of the proposed LNA and the L-CSLNA at the same power consumption level and output load condition. The LNAs were designed to have the same input matching at the frequency of interest. The proposed LNA shows a much better gain performance. The gain of the LNA is 3 dB higher than that of the L-CSLNA. The bandwidth (BW) decreases as the effective gain of the matching network is increased. However, as shown, the BW of the LNA in this simulation is still sufficiently large for the required standard.

The noise factor of the proposed LNA is:

Compared to Equation 11, the noise contribution of R_Lg has been increased due to the π-network. However, when the LNA is designed such that G_{eff_π} is higher than G_{eff_no_L}, the noise contribution from  can be reduced. Therefore it can compensate for the loss caused by R_Lg . Moreover, the noise contribution of the cascode stage is also reduced when G_{eff_π} is increased. For a narrow band LNA at frequency f₀, the design steps are summarized as follows:

1.) Employ the smallest channel length for the best transistor performance.

2.) To achieve high gain and low noise, the value of R_f is designed to be as small as possible. However, the BW must be kept sufficient for the required application as discussed. In addition, when R_f decreases, the required L₁ is reduced, but the required C_g increases. As the negative plate of C_g is connected directly to ground, its value should not be too large.

3.) Derive the value of C_g and L₁ from Equation 12.

4.) Determine the value of L_f according to the desired gain and the available chip area. The larger L_f is, the higher the gain gets. C_f resonates with L_f at f₀.

5.) Given a specific drain current and the desired R_f and C_f value, design the transistor size and biasing according to Equations 6-9.

To verify the theory, an LNA was designed and fabricated using the IBM 0.13 μm Rf CMOS technology. Its schematic is shown in Figure 3(a). All inductors are on chip. Inductor L_L will resonate with the total capacitance at the drain node of transistor M₂ at the frequency of interest. Inductors L_g and capacitor C_g are designed to satisfy the matching condition. The second stage of this LNA is an output buffer. The output buffer was designed to match the output port to the 50 Ω load of the measuring equipment. The loading effect of the buffer is about the same as the mixer loading effect on the LNA stage.

Measurement Results

A micrograph of the LNA’s chip is shown in Figure 5. The total area including the output buffer and pads is 0.74 × 0.84 mm. Figure 6 shows the voltage gains, S₁₁ and S₂₂, of the proposed LNA. An L-CSLNA, with the same power consumption level and output load condition than the proposed LNA, was also fabricated. The LNA’s voltage gain at 2.4 GHz is 21.5 dB, while the L-CSLNA’s voltage gain is 18.8 dB. The measured gain of the LNA is 2.7 dB higher than that of the L-CSLNA. The proposed LNA has good input and output matching. The S₁₁ value is -12 dB and the S₂₂ value is -16 dB at 2.4 GHz. The corresponding NF is 4.9 dB as shown in Figure 7. The measured NF exceeded the simulated NF by 1 dB. This large difference is attributed to the poor noise modeling and process variation. An IEEE.802.15.4 receiver can tolerate a noise factor of the LNA and the mixer of 11.2 or 10.5 dB.¹ This requires a mixer of NF less than 19.8 dB if our LNA is used in the receiver front end. Such a relaxed NF requirement is not difficult to achieve in present CMOS mixer designs. The IIP3 of the LNA is -12 dBm. The core LNA draws 0.6 mA from a 1 V voltage supply. The total power consumption is only 0.6 mW.

The comparisons of this LNA with results published in the literature are summarized in Table 1. A few LNAs^11-14 have better NF but consume much more power than the proposed one. Moreover, such low NF is not necessary for the application,¹ and the performance is quite comparable with the proposed one. However, this LNA used a large resistive load to achieve high gain. Therefore, it cannot operate at a low supply voltage such as 1 V. Some of the LNAs^13,14 show a trade-off between gain and linearity. Their IIP3 is higher, but the power consumption is much higher and the gain is much lower than the proposed LNA. Based on the FOMs calculated in Table 1, this LNA has the best FOM1 and an acceptable FOM2.

Conclusion

A new input matching topology, without gain trade-off for the CSLNA, was presented. The input network is realized using a capacitive feedback and a π-network. Based on this method, the CSLNA is able to achieve higher gain, while maintaining good input matching and low power consumption. The design method was explained and the LNA was designed and fabricated. The need of source inductor L_s is eliminated and higher gain was achieved when compared to the L-CSLNA. The proposed LNA consumes only 0.6 mW, while providing very high gain, good input matching and moderate NF.

References

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Thi Thu Nga Tran received her bachelor of engineering degree (Hons.) in electronics from Nanyang Technological University (NTU), Singapore, in 2008. Currently, she is working towards her doctorate in philosophy degree at NTU, Singapore. Her research interests include ultra-low power R_f front-end IC design and mixed-signal circuits for high speed applications.

Chirn Chye Boon received his bachelor of engineering (Hons.) (Elect.) in 2000 and his Ph.D. (Elect. Eng.) in 2004 from Nanyang Technological University (NTU), Singapore. In 2005, he joined NTU as a Research Fellow and became an assistant professor in the same year. Before that, he was with Advanced RFIC, where he worked as a senior engineer. He specializes in the areas of radio frequency & MM-wave circuits and systems design for biomedical and communications applications.

Manh Anh Do received his bachelor of engineering (Hons.) degree and his doctorate in philosophy degree in electrical engineering from the University of Canterbury, Christchurch, New Zealand, in 1973 and 1977, respectively. Between 1977 and 1989, he held various positions, including design engineer, production manager, and research scientist in New Zealand. He was a senior lecturer with the National University of Singapore, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, as a senior lecturer in 1989 and obtained the Associate Professorship in 1996 and Professorship in 2001. Between 1995 and 2005, he was Head of division of circuits and systems, NTU. He was the director of center for integrated circuits and systems from 2007 to 2010. He is currently a member of the NTU Research Council. His current research interests include mobile communications, RFIC design and mixed-signal circuits.

Kiat Seng Yeo received his bachelor of engineering (Hons.) (Elect.) in 1993, and his doctorate in philosophy (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He began his academic career as a lecturer in 1996, and was promoted to assistant professor in 1999 and then to associate professor in 2002. He was Sub-Dean (Student Affairs) from 2001 to 2005. He is a board member of Microelectronics IC Design and Systems Association of Singapore, Member of the Advisory Committee of the Centre for Science Research & Talent Development of Hwa Chong Institution and consultant to statutory boards and multinational corporations in the areas of IC design.