Thales' Land & Joint Systems Division has awarded RF Engines (RFEL), the experts in signal processing for FPGA, a contract for the supply of a complex channeliser design. Building on the successful launch of the ChannelCore product line in December of 2005, this contract calls for a modified version of that product to meet a specific channel plan and FPGA resource availability. The use of this design has enabled Thales to utilize a small FPGA in the project, therefore meeting both space and power consumption targets.
The RFEL design will form a key part of a new high specification, digital receiver system that Thales is developing. Multiple instantiations of the design will be included in a single Altera Stratix-II device, and so a highly efficient structure is required, with critical timing and low power usage. It is essential that the design fully exploits the architecture of the Stratix-II device.
The overall system design approach will allow for future upgrading of the system to accommodate developments in analogue to digital converters and other device enhancements, and so the RFEL channeliser design has also been structured in such a way as to accommodate these overall system changes.
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