Microwave Journal
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Integrated Transceivers Simplify Design, Improve Phased Array Radar Performance

January 13, 2020

Phased array radar systems use many transmit (Tx) and receive (Rx) channels to create steerable beams. Historically, these platforms were built using separate Tx and Rx ICs, including separate digital-to-analog converters (DAC) in the Tx chain and analog-to-digital converters (ADC) in the Rx chain. The use of discrete ICs led to large footprint, high-power consumption, high cost systems with long time to market, due partially to the manufacturing and calibration complexities. A newer approach uses integrated transceivers that combine the discrete functions into a single IC, enabling smaller, lower power consumption and lower cost phased array radar platforms with faster time to market. This article will discuss the benefits enabled by integration.

Integrated transceivers combine multiple functions onto a single IC, simplifying system design and streamlining a customer’s time to market. The latest transceivers integrate DACs, ADCs, local oscillator (LO) synthesizers, microprocessors, mixers and more functions into a single monolithic chip, such as Analog Devices’ 12 mm x 12 mm ADRV9009 (see Figure 1). This product combines two Rx channels and two Tx channels with digital signal processing (DSP) and achieves 200 MHz Rx bandwidth and a tunable Tx bandwidth of 450 MHz. An application program interface (API) is provided to program and control the transceiver from the customer’s platform. Gain and attenuation can be controlled using the on-chip front-end networks, and built-in initialization and tracking calibration routines provide the performance required for many communications and military applications.

Figure 1

Figure 1 The ADRV9009 is an example of an integrated transceiver that combines RF and digital functions on a single IC.

Figure 2

Figure 2 Phase can be aligned to a reference source with the RFPLL phase sync enabled (a) vs. disabled (b).

Figure 3

Figure 3 The number of system channels can be increased using additional transceivers.

The integrated transceiver creates all the clock signals needed for Tx and Rx, injecting a single reference clock signal known as REF_CLK. On-chip phase-locked loops synthesize all the required clocks for DAC and ADC sampling, LO generation and the microprocessor. If the internal LO phase noise does not meet system requirements, the user can inject an external LO with lower phase noise. Data from the transceiver is offloaded via a standard JESD204b multigigabit serial data interface, enabling large amounts of simultaneous data for Tx and Rx. If deterministic latency and data synchronization are needed, the user can use the built-in multichip synchronization (MCS) feature and issue a SYS_REF signal to act as a master timing reference for an initial lane alignment sequence (ILAS).1 The LO phase of a Tx or Rx channel can be deterministic with respect to a master reference phase using the built-in RFPLL phase sync feature. By using both the MCS and the RFPLL phase sync features, phase alignment can be replicated when initializing the transceiver, frequency tuning or toggling the radio on and off via the control software (see Figure 2).

MULTIPLE INTEGRATED TRANSCEIVERS

If more than two Rx and two Tx are required for a system, the user can use multiple transceivers and benefit from the small size achieved with monolithic integration (see Figure 3). Multiple transceivers can be synchronized using concurrent SYS_REF pulses to simultaneously trigger internal dividers for all the ICs. These SYS_REF pulses can be issued by either clock chips or baseband processors with programmable delays, to account for any length mismatches between the routes to the various ICs. Both the data paths and multiple LOs across multiple ICs are capable of being deterministic.



Increasing the channel count by using synchronized integrated transceivers enables these devices to serve as the backbone of a phased array radar. When combining phase- and amplitude-aligned Tx and Rx channels, using multiple integrated transceivers has demonstrated system-level dynamic range, spurious and phase noise improvements. On-chip DSP features such as numerically-controlled oscillators (NCO) and digital up-converters (DUC) or digital down-converters (DDC) enable system-level spurious decorrelation within a single IC.2

Combining Rx channels using multiple integrated transceivers has demonstrated both improved system-level noise spectral density (NSD) and spurious performance. This improves the dynamic range of a phased array radar by lowering the effective noise floor of the system while maintaining the full-scale power of the channel. Figure 4 compares the measured system performance using a 27 MHz carrier and combining eight Rx channels to effectively increase the number of bits in the array. Although there are eight total channels, there are only four uncorrelated LOs (NLO = 4) among the four transceivers used to create the eight channels. This gives a theoretical improvement in the NSD of

NSD Improvement (dB) = 10log10 (NLO ) = 10log10 (4) = 6 dB

The measured results in Figure 4 are close to theoretical. NSD and the calculated noise floor, indicated by the horizontal line in each plot, are improved by approximately 6 dB when going from one to eight channels: the calculated noise floor improves from −89.9 to −98.3 dBFS, and the NSD goes from −148 to −154 dBFS/Hz. Another benefit is the undesired image frequencies sum in an uncorrelated manner to reduce system-level spurious. This improvement can be enhanced as the number of channels increases.

Figure 4

Figure 4 Spectral performance of a single channel (a) vs. eight channels (b) using the ADRV9009 transceiver.

Figure 5

Figure 5 Transceiver phase noise comparison using the internal vs. external LOs at 2.6 GHz. A Rohde & Schwarz SMA100B signal generator was the external LO.

 

Combining multiple integrated transceiver channels and aligning the phase can improve the phase noise of the array. The top three traces of Figure 5 show improved phase noise when combining eight transmit channels using the internal LOs of four integrated transceiver ICs. Once again, with four distinct and uncorrelated LOs (NLO = 4), the phase noise is improved by approximately 6 dB when increasing the number of Tx channels from one to eight. Increasing the channel count will further improve the phase noise of the radar. Alternatively, an external LO can be injected into each subarray of N transceivers to improve the starting phase noise of the subarray, shown by the lower trace in Figure 5. However, each element within the subarray will be correlated, and the subarray will not benefit from channel summing improvements, since the elements all share the same LO.

Figure 6

Figure 6 Increasing the channel count and using digital phase shifting (a) enables the theoretical system beamwidth to be narrowed.

With its integrated DSP features such as NCOs, digital phase shifters, DUCs and DDCs, the transceivers enable baseband phase- and frequency-shifting in the digital domain, enabling digital beamforming in a multichannel phased array radar. By integrating these functions on a single IC, a transceiver-based system can support the required antenna lattice spacings for many phased array applications. Increasing channel count with more transceivers generally results in narrower beams, at the expense of increasing system footprint. However, with the multiple functions integrated in a single monolithic IC, the increase in footprint is smaller than could be achieved previously.

Simulating radiation patterns using MATLAB®, Figure 6 shows how increasing N from 23 (8) to 210 (1024) channels narrows the beam with a deeper lobe amplitude, although the achievable power nulls will be dictated by the actual antenna design.

CONCLUSION

The integration of multiple digital and analog functions within a single, small transceiver IC simplifies phased array design and accelerates development and manufacturing. These transceivers enable both digital beamforming and hybrid beamforming, depending on system specifications. This article has demonstrated the performance that can be achieved with Analog Devices’ transceiver. The ADRV9009 supports a variety of system architectures, serving multiple applications with the same hardware.n

References

  1. J. Harris, “What Is JESD204 and Why Should We Pay Attention to It?,” Analog Devices Technical Article, MS-2374, October 2013, pp. 1–4.
  2. P. Delos, M. Jones and M. Robertson, “RF Transceivers Enable Forced Spurious Decorrelation in Digital Beamforming Phased Arrays,” Analog Devices Technical Article, August 2018.