Microwave Journal
www.microwavejournal.com/articles/30267-a-20-ghz-low-phase-noise-push-push-vco-in-ingap-gaas-hbt-technology

A 20 GHz Low Phase Noise Push-Push VCO in InGaP GaAs HBT Technology

Jincan Zhang, Bo Liu, Leiming Zhang and Ligong Sun, Henan University of Science and Technology, Luoyang, China and Yuming Zhang, Hongliang Lu and Yimen Zhang, Xidian University, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi’an, China
May 13, 2018

A 20 GHz low phase noise voltage-controlled oscillator (VCO) uses InGaP GaAs heterojunction bipolar transistor (HBT) technology. A push-push negative gm VCO configuration taking its output signal from a capacitive base common node of the cross-coupled transistors is employed to achieve a high oscillation frequency and low phase noise. The VCO oscillates from 19.44 to 20.04 GHz. Measured phase noise is -111.8 dBc/Hz at 1 MHz offset from a 19.78 GHz carrier. It consumes 31 mW from a 5 V supply and occupies an area of 0.514 mm × 0.622 mm. Its figure of merit is -182.8 dBc/Hz.

The increased demand for high data-rate wireless communication is driving the development of RFIC to higher frequency bands. For high frequency RFICs, InGaP GaAs HBT technology is a good candidate. Compared with CMOS, InGaP GaAs HBTs have the advantages of potentially higher fT, higher transconductance and lower 1/f noise. In addition, InGaP GaAs HBTs have been shown to have inherent radiation hardening, making them well suited for the applications in the space environment.1-2

In transceiver systems, VCOs are key components, and most systems require low phase noise and jitter, which degrade system performance by reducing accuracy and increasing errors. At RF frequencies, two VCO topologies (cross-coupled3-6 and Colpitts7-10) are widely used. From Andreani et al.,11 it can be concluded that both topologies are capable of very good phase noise; however, it also has shown that a cross-coupled VCO can achieve lower phase noise than a Colpitts.

Figure 1

Figure 1 Negative gm differential VCO.

In order to extend the output frequency range, a frequency doubler combined with a VCO may be used, but this increases circuit complexity and power consumption. An alternative is the so called push-push oscillator,12-13 which extracts the second harmonic of the VCO core. In this type of oscillator, the desired frequency tuning range is twice that of the VCO core and there is potentially less power consumption. Depending on the node from which the second harmonic is extracted, three architectures are found in the literature. The extracting node can be the collector common node,14 base common node13 or the emitter common node.15 Compared with the collector common node and emitter common node, the base common node is most efficient at extracting all the available second harmonic from the tank.13 In this article, we describe a 20 GHz push-push negative gm VCO that takes its output signal from a capacitive base common node of the cross-coupled transistors.

CIRCUIT DESIGN

Architecture

The circuit schematic of a conventional negative gm differential oscillator is shown in Figure 1. The cross-coupled transistors (Q1 and Q2) generate a negative gm to overcome tank loss. The capacitive voltage divider, composed of C1 and C2 + CBE (CBE is the base-emitter junction capacitor of Q1), is designed to attain an approximate loop gain of three in order to maximize the tank swing and simultaneously optimize signal amplitudes at the base nodes to feed back from the collectors of Q1. It is known that phase noise degrades rapidly if the base-voltage swing becomes larger than a certain optimum value since Q1 enters deep saturation.16

Figure 2

Figure 2 Base-emitter voltage and base current waveforms.

The common node (CN) of the capacitive voltage divider can be regarded as a virtual ground for the fundamental frequency (ωo) just like the emitter common node (EN), but that CN could be a very effective summing node for the second harmonics (2ωo) of the fundamental signals (V+, V-) of the VCO core. Note that the CN can be regarded as a base common node compared with the conventional emitter or collector common node. The advantage of using the CN for output extraction is that it does not require any additional circuitry such as frequency doubler to create 2ωo, other than the conventional negative gm oscillator circuit, and does not reduce the common-mode impedance at node EN. It has been reported that an additional inductance inserted between node EN and the tail current source Io can increase the common-mode impedance and the signal swing at node EN, but it is at the cost of an additional bulky inductor.

Operating Principle

The mechanisms responsible for second harmonic generation at the VCO core are investigated to understand circuit operation. A simple 20 GHz VCO is designed based on the circuit schematic of Figure 1 with a 10 GHz LC tank. The first is the nonlinear switching characteristics of the base-emitter junction diode. Although the circuit operates nonlinearly, it is helpful to use linear circuit analysis when appropriate.

Figure 2 illustrates the simulated waveforms of the base-emitter voltage (VBE) and the base input current (IB) of Q1. The base current leads the base-emitter voltage by 90 degrees due to the base input capacitance, and the upper half period of VBE is distorted compared with the undistorted sinusoidal waveform. The distortion is due to the exponential current-voltage relationship of the base-emitter junction diode given by

Figure 3

Figure 3 Base-emitter voltage waveform distortion.

Math 1

where Is is the saturation current and VT is the thermal voltage. Figure 3 illustrates conceptually how the upper half period of VBE is distorted by voltage clipping when the base current is a large sinusoidal signal.

The second cause for second harmonic generation is the different time constants involved in charging and discharging the base-emitter junctions in the circuit. Again, a linear circuit analysis provides an intuitive understanding. The time constant at the base-emitter nodes is given by

Math 2

where RB is the base input resistance. As shown in Figure 4, in region I, IB is high, i.e., RB is small, so that the corresponding τ is small. This results in a fast rise time. The inverse occurs in region II.

Figure 4

Figure 4 Rise and fall times of the base-emitter voltage vs. τ.

Figure 5

Figure 5 Voltage at the capacitive common node (CN).

These two mechanisms, together, contribute to second harmonic generation in the base-voltage waveform. When they are summed at the capacitive CN, the fundamental components at ωo cancel out due to their 180 degree phase difference and only the second harmonic components add constructively. This results in 2ωo at the output as shown in Figure 5. Moreover, the amplitude of the voltage waveform at the capacitive CN is not divided down by the capacitive divider. By contrast, the differential-mode fundamental signals V+ and V- are reduced by the same capacitive divider. Therefore, the CN node is capable of extracting all the available second harmonic components very efficiently from the tank.13

MEASUREMENT RESULTS

The technology used in this work is the InGaP GaAs HBT process from WIN Semiconductors Corporation. The process offers four types of NPN transistors, Q1H051B1, Q1H101B1, Q1H151B1 and Q1H201B1, with different emitter lengths (5, 10, 15 and 20 μm, respectively). Main electrical properties for NPN transistors are the collector-emitter breakdown voltage BVCEO = 9 V, the maximum unity current gain frequency fT = 65 GHz and the maximum unity power gain frequency fmax = 80 GHz. Passive components, including two metal layers, two types of capacitors, resistors, varactor diodes and inductances, as well as back side via holes are available in the process. Passive and active device models have been implemented and validated by simulation with Keysight Advanced Design System (ADS) software.



Figure 6 shows a micrograph with a chip area of 0.514 mm × 0.622 mm, including all test pads. The circuit is measured on wafer. An HP4142B voltage and current source is used to supply the DC voltages and the output is connected through a ground-signal-ground probe to the Keysight N9030A spectrum analyzer with a phase noise measurement utility and a 50 Ω load. The VCO is biased with VDD = 5 V and IDD = 6.2 mA. It consumes 31 mW of DC power.

Figure 6

Figure 6 VCO IC.

Figure 7

Figure 7 Simulated and measured VCO frequency vs. tuning voltage.

The oscillation frequency variation as a function of control voltage is plotted in Figure 7. When the control voltage is tuned from 0 to 5 V, the VCO operates from 20.04 to 19.44 GHz. That is, the VCO exhibits a tuning range of 3.04 percent based on a 19.74 GHz center frequency. The measured oscillation frequency (20.04 to 19.44 GHz) of the VCO is shifted down slightly as compared to the simulated oscillation frequency (20.92 to 20.2 GHz). The difference between the simulated and measured results can be attributed to the fact that all the passive elements and wiring of circuit were modeled with the quasi 3D electromagnetic simulation of momentum electromagnetic (EM) simulator in ADS. It is difficult to set the substrate parameters to be the same as those fabricated from the list in the library. Figure 8 shows the measured signal output power, which is above -10 dBm over the output frequency range.

Figure 8

Figure 8 Measured VCO output power vs. tuning voltage.

Figure 9

Figure 9 Measured VCO phase noise.

Phase noise of the VCO is difficult to measure, due to spectrum jitter caused by noise from supply and tuning voltages. In this work, the phase noise is roughly measured using the Keysight N9030A phase noise utility. Figure 9 shows the measured results. VCO phase noise is -111.8 dBc/Hz at 1 MHz offset from the 19.78 GHz carrier frequency.

Table 1

Table 1 compares this performance with that of previously reported VCOs in K- and Ka-Band. The commonly used figure of merit (FOM), which accounts for phase noise (PN), oscillation frequency (fosc), frequency offset (△f) from fosc, and power dissipation (PVCO) as depicted in Equation 3,6 is used for the comparison.

Math 3

It is evident from Table 1 that, the VCO reported in this work has an excellent FOM compared with the other oscillators processed in SiGe BiCMOS or CMOS technology. Furthermore, its power consumption is remarkably low, only 31 mW, compared with other VCOs realized in the same InGaP GaAs HBT technology.17-18

CONCLUSION

A K-Band VCO in InGaP GaAs HBT technology operates at a high oscillation frequency with low phase noise. It employs a push-push negative gm architecture, which takes its output signal from a capacitive base CN of the cross-coupled transistors. Measurements demonstrate an oscillation frequency range from 19.44 to 20.04 GHz. Phase noise is -111.8 dBc/Hz at 1 MHz
offset from 19.78 GHz carrier.

ACKNOWLEDGMENT

This project is supported by the National Basic Research Program of China (Grant No. 2010CB327505), the Advance Research project of China (Grant No. 51308xxxx06), the Advance Research Foundation of China (Grant No. 9140A08xxxx11DZ111), the Doctoral Scientific Research Foundation of Henan University of Science and Technology (Grant No. 400613480011) and the Foundation of He’nan Educational Committee (Grant No. 15A510001).

References

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Jincan Zhang received his M.S. degree and Ph.D. degrees from Xi’an University of Technology in 2010 and 2014, respectively. He is currently a lecturer at Henan University of Science and Technology. His research is focused on modeling of HBTs and the design of very high speed integrated circuits.

Hongliang Lu received her M.S. and Ph.D. degrees in microelectronics engineering from Xidian University in 2003 and 2007, respectively. Since 2010, she has been a professor in the School of Microelectronics at Xidian University. Her work involves modeling and experiments on SiC MESFETs and other devices.

Yuming Zhang received his M.S. and Ph.D. degrees in microelectronics engineering from Xidian University and Xi’an Jiaotong University in 1992 and 1998, respectively. From 1999 to 2000, he was with Rutgers University as a postdoctoral fellow. Since 2001, he has been a professor at the Microelectronics Institute, Xidian University. His research is in the design, modeling, fabrication and electrical characterization of SiC electronic devices for high temperature and high-power operation.

Yimen Zhang is a professor of the School of Microelectronics, Xidian University. He has been a visiting scholar and senior visiting scholar at Arizona State University, Tempe, and Yale University, respectively. His research interests are in the areas of wideband semiconductor devices, semiconductor devices modeling, TCAD for VLSI and quantum well devices.

Bo Liu received his B.E., M.S. and D.E. degrees in electronic engineering from the University of Kitakyushu, Japan in 2005, 2008 and 2012, respectively. Since 2012, he has been an associate professor at Henan University of Science and Technology. His research interests include VLSI layout design and process variation analysis for analog IC design for manufacturability.

Leiming Zhang received his M.S. degree at the University of Electronic Science and Technology of China in 2008. He is currently a lecturer at Henan University of Science and Technology. His research is focused on device modeling of CMOS and design of mixed signal integrated circuits.

Ligong Sun received his M.S. degree from Henan University of Science and Technology in 2006. He is currently an associate professor in Henan University. His research is focused on AI and robot, computer application technology and the design of mixed-signal integrated circuits.